as7c32098a Alliance Memory, Inc, as7c32098a Datasheet - Page 7

• Manufacturer Part Number: as7c32098a
• Description: 3.3 V 128k ? 16 Cmos Sram
• Manufacturer: Alliance Memory, Inc

Write waveform 3
AC test conditions
Notes
1
2
3
4
5
6
7
8
9
10 C=30pF, except on High Z and Low Z parameters, where C=5pF.
- Output load: see Figure B.
- Input pulse level: GND to 3.0V. See Figure A.
- Input rise and fall times: 2 ns. See Figure A.
- Input and output timing reference levels: 1.5V.
2/17/06, v 1.1
During V
For test conditions, see AC Test Conditions, Figures A and B.
t
This parameter is guaranteed, but not tested.
WE is High for read cycle.
CE and OE are Low for read cycle.
Address valid prior to or coincident with CE transition Low.
All read cycle timings are referenced from the last valid address to the first transitioning address.
All write cycle timings are referenced from the last valid address to the first transitioning address.
CLZ
+3.0V
Data
Address
and t
GND
LB, UB
Data
CC
WE
OUT
CHZ
CE
IN
power-up, a pull-up resistor to V
10%
are specified with C
Figure A: Input pulse
90%
9
2 ns
t
AS
L
High Z
90%
= 5pF as in Figure B. Transition is measured ±500mV from steady-state voltage.
10%
CC
on CE is required to meet I
Alliance Semiconductor
D
Figure B: 3.3V Output load
OUT
350Ω
Data undefined
t
AW
t
WZ
t
t
t
WC
CW
BW
SB
t
DW
+3.3V
320Ω
C
GND
specification.
t
®
WP
10
Thevenin equivalent:
Data valid
High Z
t
t
WR
t
AH
DH
D
OUT
168Ω
AS7C32098A
+1.728V
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