as6c8008 Alliance Memory, Inc, as6c8008 Datasheet - Page 5

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as6c8008

Manufacturer Part Number
as6c8008
Description
1024k X 8 Bit Super Low Power Cmos Sram
Manufacturer
Alliance Memory, Inc
Datasheet

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0
TIMING WAVEFORMS
READ CYCLE 1 (Address Controlled) (1,2)
READ CYCLE 2 (CE# and CE2 and OE# Controlled) (1,3,4,5)
Notes :
1.WE# is high for read cycle.
2.Device is continuously selected OE# = low, CE# = low
3.Address must be valid prior to or coincident with CE# = low
4.t
5.At any given temperature and voltage condition, t
Address
Address
CLZ
Dout
Dout
CE#
CE2
OE#
JANUARY/2008, V 1.0
January 2007
JANUARY 2008
, t
OLZ
, t
CHZ
and t
Previous Data Valid
OHZ
are specified with C
High-Z
1024K X 8 BIT SUPER LOW POWER CMOS SRAM
t
CLZ
t
t
AA
AA
L
t
= 5pF. Transition is measured ±500mV from steady state.
OLZ
t
ACE
CHZ
t
t
Alliance Memory Inc.
RC
RC
t
OE
is less than t
.,
CE2 = high
,
CE2 = high; otherwise t
512K X 8 BIT LOW POWER CMOS SRAM
CLZ
.
, t
OHZ
Data Valid
is less than t
Data Valid
AA
t
OH
t
CHZ
is the limiting parameter.
t
OLZ.
OHZ
t
OH
High-Z
Page 5 of 11
AS6C8008

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