gs9023-cfy ETC-unknow, gs9023-cfy Datasheet - Page 7

• Manufacturer Part Number: gs9023-cfy
• Description: Embedded Audio Codec
• Manufacturer: ETC-unknow

DETAILED DESCRIPTION
The GS9023 has two main modes of operation: Multiplex
Mode and Demultiplex Mode. In Multiplex Mode, which is
selected by setting the DEMUX/MUX input pin LOW, digital
audio is embedded into a digital video stream. In
Demultiplex Mode, which is selected by setting the DEMUX/
MUX input pin HIGH, digital audio is extracted from a digital
video stream. Tables 14 and 15 contain Host Interface
Register descriptions for the Multiplex and Demultiplex
Modes respectively.
MULTIPLEX MODE
Video Clock Input
A master video clock must be supplied to the PCLK pin
corresponding to the selected video standard. The
supported video input standards and corresponding clock
frequencies are listed in Table 1.
Video Data Input
The video data DIN[9:0] is clocked into the GS9023 on the
rising edge of PCLK. The video clock frequency must
correspond to the video input standard selected. This is
done via the “VSEL” bit of Host Interface Register #0h.
TABLE 1: Video Input Formats
GENNUM CORPORATION
525/D2 (SMPTE259M)
525/D2 (SMPTE244M)
525/D1
Reserved
525/16:9
Reserved
525/4:4:4:4 (System #1)
Reserved
625/D2 (with TRS)
625/D2 (without TRS)
625/D1
Reserved
625/16:9
Reserved
625/4:4:4:4 (System #2)
625/4:2:2P (System #4)
VIDEO STANDARD
SERIAL DIGITAL
DATA RATE
(Mbps)
143
143
270
360
540
177
177
270
360
540
540
-
-
-
-
-
FREQUENCY
(MHz)
PCLK
14.3
14.3
27.0
36.0
54.0
17.7
17.7
27.0
36.0
54.0
54.0
-
-
-
-
-
7
When “VSEL” is LOW, the video input standard is selected
by the VM[2:0] and TRS input pins. When “VSEL” is HIGH,
the video input standard is selected by the “VMOD[2:0]”
and “D2_TRS” bits in Host Interface Register #0h. The
supported video input standards are listed in Table 1.
After the user has specified the video input standard via the
VM[2:0] and TRS pins or by setting Host Interface
Register #0h, the GS9023 performs video standard
detection to verify that the input video stream corresponds
to the selected standard. When the selected video input
standard is verified, the “VXST” bit of Host Interface
Register #0h is set HIGH. The LOCK output pin and the
“LOCK” bit of Host Interface Register #0h are then set
HIGH if at least one of the audio channel enable bits
“CHACT(4-1)” of Host Interface Register #1h is HIGH and
the start of a video frame is detected.
NOTE: The user must ensure that the video input format
correctly corresponds to the video format being provided to
the GS9023.
“VMOD[2]”
VM[2] or
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
“VMOD[1]”
VM[1] or
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
“VMOD[0]”
VM[0] or
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
“D2_TRS”
TRS or
522 - 45 - 05
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1