74AHC14BQ,115 NXP Semiconductors, 74AHC14BQ,115 Datasheet

IC HEX INV SCHMITT TRIG 14DHVQFN

74AHC14BQ,115

Manufacturer Part Number
74AHC14BQ,115
Description
IC HEX INV SCHMITT TRIG 14DHVQFN
Manufacturer
NXP Semiconductors
Series
74AHCr
Datasheet

Specifications of 74AHC14BQ,115

Number Of Circuits
6
Logic Type
Inverter with Schmitt Trigger
Package / Case
14-VQFN Exposed Pad, 14-HVQFN, 14-SQFN, 14-DHVQFN
Number Of Inputs
1
Current - Output High, Low
8mA, 8mA
Voltage - Supply
2 V ~ 5.5 V
Operating Temperature
-40°C ~ 125°C
Mounting Type
Surface Mount
Logic Family
74AHC
High Level Output Current
- 8 mA
Low Level Output Current
8 mA
Propagation Delay Time
11 ns
Supply Voltage (max)
5.5 V
Supply Voltage (min)
2 V
Maximum Operating Temperature
+ 125 C
Minimum Operating Temperature
- 40 C
Input Level
CMOS
Mounting Style
SMD/SMT
Operating Supply Voltage
5 V
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Lead Free Status / RoHS Status
Lead free / RoHS Compliant, Lead free / RoHS Compliant
Other names
568-2498-2
935273779115
1. General description
2. Features
The 74AHC14; 74AHCT14 is a high-speed Si-gate CMOS device and is pin compatible
with Low-power Schottky TTL (LSTTL). It is specified in compliance with JEDEC standard
No. 7A.
The 74AHC14; 74AHCT14 provides six inverting buffers with Schmitt-trigger action. They
are capable of transforming slowly changing input signals into sharply defined, jitter-free
output signals.
I
I
I
I
I
I
I
74AHC14; 74AHCT14
Hex inverting Schmitt trigger
Rev. 05 — 4 May 2009
Balanced propagation delays
All inputs have Schmitt-trigger actions
Inputs accept voltages higher than V
Input levels:
ESD protection:
Multiple package options
Specified from 40 C to +85 C and from 40 C to +125 C
N
N
N
N
N
For 74AHC14: CMOS level
For 74AHCT14: TTL level
HBM EIA/JESD22-A114E exceeds 2000 V
MM EIA/JESD22-A115-A exceeds 200 V
CDM EIA/JESD22-C101C exceeds 1000 V
CC
Product data sheet

Related parts for 74AHC14BQ,115

74AHC14BQ,115 Summary of contents

Page 1

Hex inverting Schmitt trigger Rev. 05 — 4 May 2009 1. General description The 74AHC14; 74AHCT14 is a high-speed Si-gate CMOS device and is pin compatible with Low-power Schottky TTL (LSTTL specified in compliance with JEDEC ...

Page 2

... NXP Semiconductors 3. Ordering information Table 1. Ordering information Type number Package Temperature range Name 74AHC14 74AHC14D +125 C 74AHC14PW +125 C 74AHC14BQ +125 C 74AHCT14 74AHCT14D +125 C 74AHCT14PW +125 C 74AHCT14BQ +125 C 4. Functional diagram mna204 Fig 1. Logic symbol 74AHC_AHCT14_5 Product data sheet 74AHC14; 74AHCT14 Description SO14 plastic small outline package ...

Page 3

... NXP Semiconductors 5. Pinning information 5.1 Pinning GND 7 Fig 4. Pin configuration SO14 and TSSOP14 5.2 Pin description Table 2. Pin description Symbol Pin GND 74AHC_AHCT14_5 Product data sheet 001aac498 Fig 5. Description data input 1 data output 1 data input 2 data output 2 data input 3 data output 3 ...

Page 4

... NXP Semiconductors 6. Functional description [1] Table 3. Function table Input [ HIGH voltage level LOW voltage level. 7. Limiting values Table 4. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V). Symbol Parameter V supply voltage CC V input voltage ...

Page 5

... NXP Semiconductors 9. Static characteristics Table 6. Static characteristics At recommended operating conditions; voltages are referenced to GND (ground = 0 V). Symbol Parameter Conditions 74AHC14 V HIGH-level output voltage 4.0 mA 8.0 mA LOW-level output voltage 4.0 mA 8.0 mA input leakage GND current 5 supply current 5 input I capacitance C output O capacitance ...

Page 6

... NXP Semiconductors 10. Dynamic characteristics Table 7. Dynamic characteristics Voltages are referenced to GND (ground = 0 V); for test circuit see Symbol Parameter Conditions 74AHC14 t propagation nA to nY; see pd delay power MHz dissipation capacitance 74AHCT14 t propagation nA to nY; see pd delay power MHz dissipation capacitance ...

Page 7

... NXP Semiconductors 11. Waveforms Measurement points are given in V and V are typical voltage output levels that occur with the output load Fig 6. Input to output propagation delays Table 8. Measurement points Type 74AHC14 74AHCT14 Test data is given in Table Definitions test circuit Termination resistance should be equal to output impedance Z ...

Page 8

... NXP Semiconductors Table 9. Test data Type Input V I 74AHC14 V CC 74AHCT14 3.0 V 12. Transfer characteristics Table 10. Transfer characteristics At recommended operating conditions; voltages are referenced to GND (ground = 0 V); see Symbol Parameter Conditions 74AHC14 V positive-going threshold voltage negative-going threshold ...

Page 9

... NXP Semiconductors 1 (mA Fig 10. Typical 74AHC transfer characteristics 74AHC_AHCT14_5 Product data sheet mna411 I CC (mA ( (mA Rev. 05 — 4 May 2009 74AHC14; 74AHCT14 Hex inverting Schmitt trigger 4 mna413 6 V (V) I © NXP B.V. 2009. All rights reserved. mna412 ...

Page 10

... NXP Semiconductors (mA 4 Fig 11. Typical 74AHCT transfer characteristics 14. Application information ------------------------ - For 74AHC14 0. For 74AHCT14: T Fig 12. Relaxation oscillator 74AHC_AHCT14_5 Product data sheet mna414 ( mna035 ------------------------ - 0.60 RC Rev. 05 — 4 May 2009 74AHC14; 74AHCT14 Hex inverting Schmitt trigger (mA 5 mna415 6 V (V) I © NXP B.V. 2009. All rights reserved. ...

Page 11

... NXP Semiconductors 15. Package outline SO14: plastic small outline package; 14 leads; body width 3 pin 1 index 1 e DIMENSIONS (inch dimensions are derived from the original mm dimensions) A UNIT max. 0.25 1.45 mm 1.75 0.25 0.10 1.25 0.010 0.057 inches 0.01 0.069 0.004 0.049 Note 1. Plastic or metal protrusions of 0.15 mm (0.006 inch) maximum per side are not included. ...

Page 12

... NXP Semiconductors TSSOP14: plastic thin shrink small outline package; 14 leads; body width 4 pin 1 index 1 e DIMENSIONS (mm are the original dimensions) A UNIT max. 0.15 0.95 mm 1.1 0.25 0.05 0.80 Notes 1. Plastic or metal protrusions of 0.15 mm maximum per side are not included. 2. Plastic interlead protrusions of 0.25 mm maximum per side are not included. ...

Page 13

... NXP Semiconductors DHVQFN14: plastic dual in-line compatible thermal enhanced very thin quad flat package; no leads; 14 terminals; body 2 0.85 mm terminal 1 index area terminal 1 index area DIMENSIONS (mm are the original dimensions) (1) A UNIT max. 0.05 0. 0.2 0.00 0.18 Note 1. Plastic or metal protrusions of 0.075 mm maximum per side are not included. ...

Page 14

... NXP Semiconductors 16. Abbreviations Table 11. Abbreviations Acronym Description CDM Charged Device Model CMOS Complementary Metal-Oxide Semiconductor DUT Device Under Test ESD ElectroStatic Discharge HBM Human Body Model LSTTL Low-power Schottky Transistor-Transistor Logic MM Machine Model 17. Revision history Table 12. Revision history Document ID Release date ...

Page 15

... Right to make changes — NXP Semiconductors reserves the right to make changes to information published in this document, including without limitation specifications and product descriptions, at any time and without notice ...

Page 16

... NXP Semiconductors 20. Contents 1 General description . . . . . . . . . . . . . . . . . . . . . . 1 2 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 3 Ordering information . . . . . . . . . . . . . . . . . . . . . 2 4 Functional diagram . . . . . . . . . . . . . . . . . . . . . . 2 5 Pinning information . . . . . . . . . . . . . . . . . . . . . . 3 5.1 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 5.2 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 3 6 Functional description . . . . . . . . . . . . . . . . . . . 4 7 Limiting values Recommended operating conditions Static characteristics Dynamic characteristics . . . . . . . . . . . . . . . . . . 6 11 Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 12 Transfer characteristics Transfer characteristics waveforms Application information ...

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