th71221 Melexis Company, th71221 Datasheet - Page 5
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th71221
Manufacturer Part Number
th71221
Description
Transceiver - 27 To 930mhz, Fsk/fm/ask, Multi-channel 32l Qfn 5x5 Quad
Manufacturer
Melexis Company
Datasheet
1.TH71221.pdf
(44 pages)
Available stocks
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Part Number
Manufacturer
Quantity
Price
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Part Number:
th71221ELQ
Manufacturer:
SANDISK
Quantity:
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1.4
1.5
The transceiver can operate in two different user modes. It can be used either as a 3wire-bus-controlled
programmable or as a stand-alone fixed-frequency device. After power up, the transceiver is set to Stand-
alone User Mode (SUM). In this mode, pins FS0/SDEN and FS1/LD must be connected to V
order to set the desired frequency of operation. There are 4 pre-defined frequency settings: 315MHz,
433.92MHz, 868.3MHz and 915MHz. The logic level at pin FS0/SDEN must not be changed after power up
in order to remain in fixed-frequency mode.
After the first logic level change at pin FS0/SDEN, the transceiver enters into Programmable User Mode
(PUM). In this mode, the user can set any PLL frequency or mode of operation by the SCI. In SUM pins
FS0/SDEN and FS1/LD are used to set the desired frequency, while in PUM pin FS0/SDEN is part of the
3-wire serial control interface (SCI) and pin FS1/LD is the look detector output signal of the PLL synthesizer.
A mode control logic allows several operating modes. In addition to standby, transmit and receive mode, two
idle modes can be selected to run either the reference oscillator only or the whole PLL synthesizer. The PLL
settings for the PLL idle mode are taken over from the last operating mode which can be either receive or
transmit mode.
The different operating modes can be set in SUM and PUM as well. In SUM the user can program the trans-
ceiver via control pins RE/SCLK and TE/SDTA. In PUM the register bits OPMODE are used to select the
modes of operation while pins RE/SCLK and TE/SDTA are part of the SCI.
39010 071221
Rev. 006
IN_LNA
25
26
OUT_PA
Block Diagram
User Mode Features
27
LNA
24
29
PA
ASK
PS_PA
28
30
21
TNK_LO
VCO
MIX
LO
counter
20
32
N
IF
VCC_PLL
31
Fig. 1:
1
23
LF
2
IFA
22
counter
RO
TH71221 block diagram
7
Page 5 of 44
VEE_PLL
R
10
1.5pF
RO
RO
FSK
11
MIX
3
19
IN_DEM
Demodulator
FSK
9
FSK/FM/ASK Transceiver
SW1
PKDET
12
Control Logic
13
15
6
OUT_DEM
SW2
16
TH71221
200k
17
27 to 930MHz
bias
18
OA1
OA2
SCI
EE
OUT_DTA
INT2/PDO
14
Data Sheet
or V
INT1
June/08
8
4
5
CC
in