cp3cn23 National Semiconductor Corporation, cp3cn23 Datasheet - Page 71
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cp3cn23
Manufacturer Part Number
cp3cn23
Description
Cp3cn23 Reprogrammable Connectivity Processor With Dual Can Interfaces
Manufacturer
National Semiconductor Corporation
Datasheet
1.CP3CN23.pdf
(246 pages)
- Current page: 71 of 246
- Download datasheet (3Mb)
15.0 12-Bit Analog to Digital Converter
The integrated 12-bit ADC provides the following features:
T 8-input analog multiplexer
T 8 single-ended channels or 4 differential channels
T External filtering capability
T 12-bit resolution with 11-bit accuracy
T Sign bit
15.1
The ADC module consists of a 12-bit ADC converter and as-
sociated state machine, together with analog multiplexers to
set up signal paths for sampling and voltage references, log-
ic to control triggering of the converter, and a bus interface.
15.1.1
Up to 8 GPIO pins may be configured as 8 singled-ended
analog inputs or 4 differential pairs. Analog/digital data
passes through four main blocks in the ADC module be-
tween the input pins and the CPU bus:
T Input Multiplexer—an analog multiplexer that selects
T Internal/External Multiplexer—an analog multiplexer
ADC0/TSX+
ADC3/TSY+
ADC1/TSY-
ADC2/TSX-
ASYNC
ADC4
ADC7
among the input channels.
that selects between the output of the Input Multiplexer
and the ADCIN external analog input.
FUNCTIONAL DESCRIPTION
Data Path
ADC_CONTROL
TOUCH_CFG
TRIGGER
Pen-Down Detector
DRV
DRV
DRV
DRV
ADC_DIV
ADC_DELAY1
MUXOUT0
MUX_CFG
DELAY1
Figure 11. Analog to Digital Converter Block Diagram
plexer
Multi-
Input
+
-
MUXOUT1 ADCIN
System
Clock
CLKDIV
Auxiliary
Clock 2
Int/Ext
ADCIN
plexer
CLKSEL
Multi-
PREF_CFG
ADC Clock
Start
71
T 15-microsecond conversion time
T Support for resistive touchscreen interface
T Internal or external start trigger
T Programmable start delay after start trigger
T Poll or interrupt on done
T 12-Bit ADC—receives the output of the Internal/External
T ADCRESLT Register—makes conversion results from
The configuration of the analog signal paths is controlled by
fields in the ADCGCR register. The Input Multiplexer is con-
trolled by the MUX_CFG field. The Internal/External Multi-
plexer is controlled by the ADCIN bit. The analog
multiplexers for selecting the voltage references used by the
ADC are controlled by the PREF_CFG and NREF_CFG
fields. The low-ohmic drivers used for interface to resistive
touchscreens are controlled by the TOUCH_CFG field.
VREFP
ADC_DELAY2
Multiplexer and performs the analog to digital conver-
sion.
the 12-Bit ADC available to the on-chip bus. The AD-
CRESLT register includes the software-visible end of a 4-
word FIFO used to queue conversion results.
DELAY2
+
-
Clock
AVCC
VREFP
ADC0
SEQUENCER
12-BIT ADC
ADC1
Control
ADC
AGND
ADCRESLT
VREFN
4-Word
ADC2
Result
FIFO
12
Pen Down
Done
ADC3
NREF_CFG
www.national.com
Wake-Up
(WUI30)
Interrupt
(IRQ13)
System
Bus
Interface
DS183
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