hsp50306 Intersil Corporation, hsp50306 Datasheet

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hsp50306

Manufacturer Part Number
hsp50306
Description
Digital Qpsk Demodulator
Manufacturer
Intersil Corporation
Datasheet

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
HSP50306
Manufacturer:
HAR
Quantity:
20 000
Part Number:
hsp50306SC-25
Manufacturer:
I
Quantity:
20 000
Part Number:
hsp50306SC-27
Manufacturer:
HARRIS
Quantity:
8
Part Number:
hsp50306SC-27
Manufacturer:
HAR
Quantity:
20 000
February 1998
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
http://www.intersil.com or 407-727-9207
Features
• 25.6MHz or 26.97MHz Clock Rates
• Single Chip QPSK Demodulator with 10kHz Tracking
• Square Root of Raised Cosine ( = 0.4) Matched
• 2.048 MBPS Reconstructed Output Data Stream
• Bit Synchronization with 3kHz Loop Bandwidth
• Internal Equalization for Multipath Distortion
• 6-Bit Real Input: Digitized 10.7MHz or 2.1MHz IF
• Level Detection for External IF AGC Loop
• 0.1s Acquisition Time
• 10
• <116mA on +5.0V Supply
Applications
• Cable Data Link Receivers
• Cable Control Channel Receivers
Ordering Information
Block Diagram
HSP50306SC-27
HSP50306SC-2796
HSP50306SC-25
HSP50306SC-2596
AGCOUT
Loop
Filtering
ADCLK
PART NUMBER
RESET
DIN0-5
CLKIN
TEST
-9
BER
6
DETECT
LEVEL
RANGE (
COS
TEMP.
0 to 70
0 to 70
0 to 70
0 to 70
LOOP FILTER
CARRIER
NCO
|
SIN
o
Copyright
C)
16 Ld SOIC
Tape and Reel
16 Ld SOIC
Tape and Reel
PACKAGE
©
Intersil Corporation 1999
GENERATOR
TIMING
M16.3
M16.3
PKG.
NO.
Q
I
8-272
LOOP FILTER
DETECTOR
BIT PHASE
BIT SYNC
Description
The HSP50306 is a 6-bit QPSK demodulator chip designed
for use in high signal to noise environments which have some
multipath distortion. The part recovers 2.048 MBPS data from
samples of a QPSK modulated 10.7MHz or 2.1MHz carrier.
The chip coherently demodulates the waveform, recovers
symbol timing, adaptively equalizes the signal to remove
multipath distortion, differentially decodes and multiplexes the
data decisions. 8-A lock signal is provided to indicate when
the tracking loops are locked and the data decisions are valid.
To optimize performance, a gain error feedback signal is
provided which can be filtered and used to close an I.F. AGC
loop around the A/D converter.
The QPSK demodulator derives all timing from CLKIN. The
chip divides this clock by 2 to provide the sample clock for the
external A/D converter. The -27 version operates at a clock
input of 26.97MHz and demodulates a 10.7MHz QPSK signal
to recover the 2048 KSPS data. The -25 version operates at a
clock input of 25.6MHz and demodulates a 2.1MHz QPSK
signal to recover the 2048 KSPS data. Variation from these
CLKIN frequencies will progressively degrade the receive
data rate, the receive IF, acquisition sweep rate, acquisition
sweep range and loop bandwidths as the deviation increases
from normal CLKIN. Details on the maximum allowable devia-
tion are found in the Input Characteristics section. The
HSP50306 processes 6-bit offset binary data. 4-bit data pro-
vides adequate performance for many applications.
HSP50306
EQUALIZER
ADAPTIVE
CARRIER
DETECT
PHASE
Digital QPSK Demodulator
4 TAP
Q
I
DECODE/
DETECT
LOCK
DIFF.
MUX
File Number
DATAOUT
LOCK
CLKOUT
4162.2

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hsp50306 Summary of contents

Page 1

... Copyright Description The HSP50306 is a 6-bit QPSK demodulator chip designed for use in high signal to noise environments which have some multipath distortion. The part recovers 2.048 MBPS data from samples of a QPSK modulated 10.7MHz or 2.1MHz carrier. The chip coherently demodulates the waveform, recovers ...

Page 2

... This signal indicates that the carrier tracking loop is locked and data on the DOUT pin should be valid. RESET 5 I This input is provided to for initialization and test. Active low. TEST 6 I This input is provided for test. Pull high for normal operation. HSP50306 16 LEAD SOIC TOP VIEW AGCOUT ...

Page 3

... Table 1 details the BER, Acquisition and Delay Performance Specifications of the HSP50306 QPSK demodulator chip, based on an input that complies with the specifications detailed in Table 2. (25.6MHz) HSP50306 26.97MHz OSC ...

Page 4

... Each pair of input bits is encoded into a phase change relative to the previous symbol. In the HSP50306, the symbol to symbol phase change is decoded into the transmitted bit pair which is multiplexed into the output data stream. ...

Page 5

... IF of the -25 version has inherently lower internal pro- cessing spectral spurs than the -27 version. Note that the receive IF for the HSP50306SC-27 is the input IF to the demod- ulator. For the HSP50306SC-25, the receive IF is 10.7MHz, but the processing is done on the spectral image at 2.1MHz. Exam- ine the spectral inversion between the 10 ...

Page 6

... NOTES: 5. Power supply current is proportional to frequency. Typical rating is 4mA/MHz. 6. Output load per test circuit and C = 40pF Not tested, but characterized at initial design and at major process/design changes. HSP50306 o Thermal Information C Thermal Resistance (Typical, Note 4) +0.5V SOIC Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...

Page 7

... An A/D converter with a clock to data out specification of 55ns and a data hold from clock specification of 2ns will meet these requirements at an oscillator clock frequency of 26.97MHz. Intersil recommends the CA3304 or CA3306 A/D con- verters for use with the HSP50306. 10. Controlled via design or process parameters and not directly tested. Characterized upon initial design and at major process or design changes ...

Page 8

... However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see web site http://www.intersil.com HSP50306 t CL ...

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