74AHC30PW,112 NXP Semiconductors, 74AHC30PW,112 Datasheet
74AHC30PW,112
Specifications of 74AHC30PW,112
935264187112
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74AHC30PW,112 Summary of contents
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NAND gate Rev. 03 — 26 June 2009 1. General description The 74AHC30; 74AHCT30 is a high-speed Si-gate CMOS device and is pin compatible with Low-power Schottky TTL (LSTTL specified in compliance with JEDEC standard ...
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... NXP Semiconductors 4. Functional diagram mna488 Fig 1. Logic symbol Fig 3. Logic diagram 74AHC_AHCT30_3 Product data sheet Y 8 Fig Rev. 03 — 26 June 2009 74AHC30; 74AHCT30 8-input NAND gate 1 & mna489 IEC logic symbol Y mna490 © NXP B.V. 2009. All rights reserved ...
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... NXP Semiconductors 5. Pinning information 5.1 Pinning 74AHC30 74AHCT30 GND Fig 4. Pin configuration SO14 and TSSOP14 5.2 Pin description Table 2. Pin description Symbol Pin GND n. 74AHC_AHCT30_3 Product data sheet n. n. 001aai162 Fig 5. Description data input data input data input ...
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... NXP Semiconductors 6. Functional description [1] Table 3. Function table Input [ HIGH voltage level LOW voltage level don’t care. 7. Limiting values Table 4. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V). Symbol Parameter V supply voltage ...
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... NXP Semiconductors 8. Recommended operating conditions Table 5. Recommended operating conditions Voltages are referenced to GND (ground = 0 V). Symbol Parameter V supply voltage CC V input voltage I V output voltage O T ambient temperature amb t/ V input transition rise and fall rate 9. Static characteristics Table 6. Static characteristics At recommended operating conditions ...
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... NXP Semiconductors Table 6. Static characteristics At recommended operating conditions; voltages are referenced to GND (ground = 0 V). Symbol Parameter Conditions C output O capacitance 74AHCT30 V HIGH-level input voltage V LOW-level input voltage V HIGH-level output voltage 8 LOW-level output voltage 8 input leakage GND current 5 supply current V ...
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... NXP Semiconductors Table 7. Dynamic characteristics Voltages are referenced to GND (ground = 0 V); for test circuit see Symbol Parameter Conditions C power MHz dissipation V = GND capacitance 74AHCT30 4 5 propagation delay see Figure power MHz dissipation V = GND capacitance [1] Typical values are measured at nominal supply voltage (V ...
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... NXP Semiconductors Test data is given in Table Definitions for test circuit termination resistance should be equal to the output impedance load capacitance including jig and probe capacitance. L Fig 7. Load circuitry for measuring switching times Table 9. Test data Type Input V I 74AHC30 V CC 74AHCT30 3.0 V ...
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... NXP Semiconductors 12. Package outline SO14: plastic small outline package; 14 leads; body width 3 pin 1 index 1 e DIMENSIONS (inch dimensions are derived from the original mm dimensions) A UNIT max. 0.25 1.45 mm 1.75 0.25 0.10 1.25 0.010 0.057 inches 0.01 0.069 0.004 0.049 Note 1. Plastic or metal protrusions of 0.15 mm (0.006 inch) maximum per side are not included. ...
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... NXP Semiconductors TSSOP14: plastic thin shrink small outline package; 14 leads; body width 4 pin 1 index 1 e DIMENSIONS (mm are the original dimensions) A UNIT max. 0.15 0.95 mm 1.1 0.25 0.05 0.80 Notes 1. Plastic or metal protrusions of 0.15 mm maximum per side are not included. 2. Plastic interlead protrusions of 0.25 mm maximum per side are not included. ...
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... NXP Semiconductors DHVQFN14: plastic dual in-line compatible thermal enhanced very thin quad flat package; no leads; 14 terminals; body 2 0.85 mm terminal 1 index area terminal 1 index area DIMENSIONS (mm are the original dimensions) (1) A UNIT max. 0.05 0. 0.2 0.00 0.18 Note 1. Plastic or metal protrusions of 0.075 mm maximum per side are not included. ...
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... NXP Semiconductors 13. Abbreviations Table 10. Abbreviations Acronym Description CDM Charged Device Model CMOS Complementary Metal-Oxide Semiconductor DUT Device Under Test ESD ElectroStatic Discharge HBM Human Body Model LSTTL Low-power Schottky Transistor-Transistor Logic MM Machine Model 14. Revision history Table 11. Revision history Document ID Release date ...
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... Right to make changes — NXP Semiconductors reserves the right to make changes to information published in this document, including without limitation specifications and product descriptions, at any time and without notice ...
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... NXP Semiconductors 17. Contents 1 General description . . . . . . . . . . . . . . . . . . . . . . 1 2 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 3 Ordering information . . . . . . . . . . . . . . . . . . . . . 1 4 Functional diagram . . . . . . . . . . . . . . . . . . . . . . 2 5 Pinning information . . . . . . . . . . . . . . . . . . . . . . 3 5.1 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 5.2 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 3 6 Functional description . . . . . . . . . . . . . . . . . . . 4 7 Limiting values Recommended operating conditions Static characteristics Dynamic characteristics . . . . . . . . . . . . . . . . . . 6 11 Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 12 Package outline . . . . . . . . . . . . . . . . . . . . . . . . . 9 13 Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . . 12 14 Revision history ...