adf7012 Analog Devices, Inc., adf7012 Datasheet - Page 12

• Manufacturer Part Number: adf7012
• Description: Multichannel Ism Band Fsk/gfsk/ook/gook/ask Transmitter
• Manufacturer: Analog Devices, Inc.

ADF7012
CIRCUIT DESCRIPTION
PLL OPERATION
A fractional-N PLL allows multiple output frequencies to be
generated from a single-reference oscillator (usually a crystal)
simply by changing the programmable N value found in the N
register. At the phase frequency detector (PFD), the reference is
compared to a divided-down version of the output frequency
(VCO/N). If VCO/N is too low a frequency, typically the output
frequency is lower than desired, and the PFD and charge-pump
combination sends additional current pulses to the loop filter.
This increases the voltage applied to the input of the VCO.
Because the VCO of the ADF7012 has a positive frequency vs.
voltage characteristic, any increase in the Vtune voltage applied
to the VCO input increases the output frequency at a rate of kV,
the tuning sensitivity of the VCO (MHz/V). At each interval of
1/PFD seconds, a comparison is made at the PFD until the PFD
and charge pump eventually force a state of equilibrium in the
PLL where PFD frequency = VCO/N. At this point, the PLL can
be described as locked.
For a Fractional N PLL
where N
CRYSTAL OSCILLATOR
The on-board crystal oscillator circuitry (Figure 27) allows an
inexpensive quartz crystal to be used as the PLL reference. The
oscillator circuit is enabled by setting XOEB low. It is enabled by
default on power-up and is disabled by bringing CE low. Errors
in the crystal can be corrected using the error correction
register within the R register.
A single-ended reference may be used instead of a crystal, by
applying a square wave to the OSC2 pin, with XOEB set high.
F
F
OUT
OUT
FRAC
VCO/N
=
=
can be bits M1 to M12 in the fractional N register.
F
F
CRYSTAL/R
R
PFD
CRYSTAL
×
R
PFD
⎛
⎜
⎝
N
×
INT
N
CP
=
+
F
Figure 26.
N
PFD
2
FRAC
12
LOOP FILTER
N
×
N
⎞
⎟
⎠
VCO
FVCO
(1)
(2)
Rev. 0 | Page 12 of 28
Two parallel resonant capacitors are required for oscillation at
the correct frequency—the value of these depend on the crystal
specification. They should be chosen so that the series value of
capacitance added to the PCB track capacitance adds to give the
load capacitance of the crystal, usually 20 pF. Track capacitance
values vary between 2 pF to 5 pF, depending on board layout.
Where possible, to ensure stable frequency operation over all
conditions, capacitors should be chosen so that they have a very
low temperature coefficient and/or opposite temperature
coefficients
CRYSTAL COMPENSATION REGISTER
The ADF7012 features a 15-bit fixed modulus, which allows the
output frequency to be adjusted in steps of FPFD/15. This fine
resolution can be used to easily compensate for initial error and
temperature drift in the reference crystal.
where F
Register. Note that the notation is twos compliment, so F11
represents the sign of the FEC number.
Example
F
F
F
FEC = −11 kHz/305.17 Hz = −36 = −(00000100100) =
11111011100 = 0x7DC
CLOCK OUT CIRCUIT
The clock out circuit takes the reference clock signal from the
oscillator section above and supplies a divided-down 50:50
mark-space signal to the CLK
2 to 30 is available. This divide is set by the DB[19:22] in the R
register. On power-up, the CLK
PFD
ADJUST
STEP
= 10 MHz
F
= 10 MHz/2
ADJUST
= −11 kHz
OSC1
STEP
= F
= FPFD/215 and FEC = Bits F1 to F11 in the R
OSC1
STEP
DIVIDER
1 TO 15
15
× FEC
= 305.176 Hz
CP2
Figure 27.
Figure 28.
OUT
CP1
÷2
OSC2
OUT
pin. An even divide from
DV
defaults to divide by 16.
DD
CLK
CLK
ENABLE BIT
OUT
OUT
(3)