adf7012 Analog Devices, Inc., adf7012 Datasheet - Page 14

• Manufacturer Part Number: adf7012
• Description: Multichannel Ism Band Fsk/gfsk/ook/gook/ask Transmitter
• Manufacturer: Analog Devices, Inc.

ADF7012
The deviation from the center frequency is set using bits D1 to
D9 in the modulation register. The frequency deviation may be
set in steps of
The deviation frequency is therefore
where ModulationNumber is set by bits D1 to D9.
The maximum data rate is a function of the PLL lock time (and
the requirement on FSK spectrum). Because the PLL lock time
is reduced by increasing the loop-filter bandwidth, highest data
rates can be achieved for the wider loop filter bandwidths. The
absolute maximum limit on loop filter bandwidth to ensure
stability for a fractional-N PLL is F
frequency, the loop bandwidth could be as high as 2.85 MHz.
FSK modulation is selected by setting bits S1 and S2 in the
modulation register low.
GFSK MODULATION
Gaussian Frequency Shift Keying, or GFSK, represents a filtered
form of frequency shift keying. The data to be modulated to RF
is prefiltered digitally using an finite impulse response filter
(FIR). The filtered data is then used to modulate the sigma-
delta fractional-N to generate spectrally-efficient FSK.
FSK consists of a series of sharp transitions in frequency as the
data is switched from one level to an other. The sharp switching
generates higher frequency components at the output, resulting
in a wider output spectrum.
With GFSK, the sharp transitions are replaced with up to 128
smaller steps. The result is a gradual change in frequency. As a
result, the higher frequency components are reduced and the
spectrum occupied is reduced significantly. GFSK does require
some additional design work as the data is only sampled once
per bit, and so the choice of crystal is important to ensure the
correct sampling clock is generated.
FSK DEVIATION
TxDATA
FREQUENCY
–F
+F
F
F
DEV
DEV
STEP
DEVIATION
(
Hz
4R
)
(
=
Hz
CHARGE
F
FRACTIONAL-N
2
PUMP
)
PFD/
PFD
14
=
F
PFD
Figure 30.
×
Σ-∆ MODULATOR
Modulation
THIRD-ORDER
PFD
2
14
/7. For a 20 MHz PFD
Number
INTEGER-N
VCO
÷N
PA STAGE
(5)
(6)
Rev. 0 | Page 14 of 28
For GFSK and GOOK, the incoming bit stream to be trans-
mitted needs to be synchronized with an on-chip sampling
clock which provides one sample per bit to the Gaussian FIR
filter. To facilitate this, the sampling clock is routed to the
TxCLK pin where data is fetched from the host microcontroller
or microprocessor on the falling edge of TxCLK, and the data is
sampled at the midpoint of each bit on TxCLK’s rising edge.
Inserting external RC LPFs on TxDATA and TxCLK lines
creates smoother edge transitions and improves spurious
performance. As an example, suitable components would be a
1 kV resistor and 10 nF capacitor for a data rate of 5 kbps.
The number of steps between symbol ‘0’ and symbol ‘1’ is
determined by the setting for the index counter.
The GFSK deviation is set up as
where m is the mod control (Bits MC1 to MC3 in the
modulation register).
The GFSK sampling clock samples data at the data rate:
where DividerFactor can be bits D1 to D7, and IndexCounter
can be bits IC1 and IC2 in the modulation register.
POWER AMPLIFIER
The output stage is based on a Class E amplifier design, with an
open drain output switched by the VCO signal. The output
control consists of six current mirrors operating as a
programmable current source.
To achieve maximum voltage swing, the RF
biased at DV
current supply to the output stage, PA biased to DV
with the correct choice of value transforms the impedance.
The output power can be adjusted by changing the value of
bits P1 to P6. Typically, this is P1 to P6 output −20dBm at 0x0,
and 13 dBm at 0x7E at 868MHz, with the optimum matching
network.
µC
GFSK
DataRate
INT
I/O
DEVIATION
DD
Figure 31. TxCLK/TxDATA Synchronization.
. A single pull-up inductor to DV
FETCH
(
bps
SAMPLE
)
(
Hz
=
FETCH
DividerFac
)
=
SAMPLE
F
PFD
FETCH
2
12
×
SAMPLE
2
tor
m
F
PFD
×
FETCH
IndexCount
OUT
pin needs to be
DD
ensures a
TxDATA
TxCLK
DD
ADF7012
er
volts, and
(7)
(8)