hs-82c54rh Intersil Corporation, hs-82c54rh Datasheet
hs-82c54rh
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hs-82c54rh Summary of contents
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... TM Data Sheet Radiation Hardened CMOS Programmable Interval Timer The Intersil HS-82C54RH is a high performance, radiation hardened CMOS version of the industry standard 8254 and is manufactured using a hardened field, self-aligned silicon gate CMOS process. It has three independently programmable and functional 16-bit counters, each capable of handling clock input frequencies 5MHz ...
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... Counter Control Word Register CHIP SELECT: A low on this input enables the HS-82C54RH to respond to RD and WR signals. RD and WR are ignored otherwise. READ: This input is low during CPU read operations. WRITE: This input is low during CPU write operations. VDD: The +5V power supply pin. A 0.1 F capacitor between pins 12 and 24 is recommended for decoupling ...
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... CONTROL WORD REGISTER AC Test Circuits OUTPUT FROM DEVICE UNDER TEST R2 NOTE: Includes stray and jig capacitance. TEST CONDITION DEFINITION TABLE TEST CONDITION 1.7V 510 3 HS-82C54RH CLK 0 COUNTER CONTROL GATE 0 0 WORD OUT 0 REGISTER CLK 1 COUNTER GATE 1 1 OUT 1 CONTROL LOGIC CLK 2 ...
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... Waveforms A0-1 TAVWL CS TSLWL DATA VALID BUS TDVWH WR FIGURE 1. WRITE TRHRL TWHWL RD, WR FIGURE 3. RECOVERY 4 HS-82C54RH A0-1 TWHAX CS RD TWHDX DATA BUS TWLWH TCHCL CLK GATE G OUTPUT 0 TCHGX TAVRL TRHAX TSLRL TRLRH TRHDZ TRLDV VALID FIGURE 2. READ TCL1CL2 TCLCH TCLCL TCH1CH2 TGHGL TGVCH ...
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... F10 17 OPEN F11 14 13 OPEN NOTES: 6. VDD = 6.5V 5% (Burn-In) 7. VDD = 6.0V 5% (Life Test IDD < 20mA 10. Resistors = 10k 11. -0.3V 12. VDD -1.0V 13. AC compliment 100kHz 10%, 50% Duty Cycle F1 = F0/ F1 F10 = F9/2 HS-82C54RH 5. N ...
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... A “low” on the RD input tells the HS-82C54RH that the CPU is reading one of the counters. A “low” on the WR input tells the HS-82C54RH that the CPU is writing either a Control Word or an initial count. Both RD and WR are qualified by CS; RD and WR are ignored unless the HS-82C54RH has been selected by holding CS low ...
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... OL. These latches normally “follow” the CE, but if a suitable Counter Latch Command is sent to the HS-82C54RH, the OL latches the present count until read by the CPU and then returns to “following” the CE. One latch at a time is enabled by the counter’ ...
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... NOTE: In all four examples, all counters are programmed to Read/Write two-byte counts. These are only four of many possible programming sequences. FIGURE 10. A FEW POSSIBLE PROGRAMMING SEQUENCES 8 HS-82C54RH and each Control Word specifies the Counter it applies to (SC0, SC1 bits), no special instruction sequence is required. Any programming sequence that follows the conventions above is acceptable ...
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... The two bytes do not have to be read one right after the other; read or write or programming operations of other Counters may be inserted between them. Another feature of the HS-82C54RH is that reads and writes of the same Counter may be interleaved; for example, if the Counter is programmed for two byte counts, the following sequence is valid. 1. Read least signifi ...
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... HS-82C54RH will not reflect the new count just written. The operation of Null Count is shown in Figure 14. A. Write to the Control Word Register: (Note 17) Null Count = 1 B. Write to the Count Register (CR): (Note 18) C. New count is loaded into CE (CR NOTES: 17. Only the Counter specified by the Control Word will have its Null Count set to 1 ...
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... X No-Operation (Three-State) FIGURE 16. READ/WRITE OPERATIONS SUMMARY Mode Definitions The following are defined for use in describing the operation of the HS-82C54RH. CLK PULSE: A rising edge, then a falling edge, in that order Counter’s CLK input. TRIGGER: A rising edge of a Counter’s Gate input. ...
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... Real Time Clock interrupt. OUT will initially be high. When the initial count has decremented HS-82C54RH OUT goes low for one CLK pulse. OUT then goes high again, the Counter reloads the initial count and the process is repeated. Mode 2 is periodic; the same sequence is repeated indefi ...
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... The above process is repeated indefinitely. So for odd counts, OUT will be high for (N + 1)/2 counts and low for (N-1)/2 counts. 13 HS-82C54RH Mode 4: Software Triggered Mode OUT will be initially high. When the initial count expires, OUT will go low for one CLK pulse then go high again.The counting sequence is “ ...
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... The upper number is the most significant byte. Since the Counter is programmed to read/write LSB only, the most significant byte cannot be read. 45. N stands for an undefined count. 46. Vertical lines show transitions between count values. FIGURE 20. MODE 3 14 HS-82C54RH WR CLK GATE OUT 0 0 ...
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... Disables counting 2) Sets output immediately high 4 1) Disables counting 5 15 HS-82C54RH Operation Common to All Modes Programming When a Control Word is written to a Counter, all Control Logic is immediately reset and OUT goes to a known initial state; no CLK pulses are required for this. Gate ...
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... D4 (4) D3 (5) D2 (6) D1 (7) D0 (8) CLK 0 (9) 16 HS-82C54RH Substrate: Radiation Hardened Silicon Gate, Dielectric Isolation Backside Finish: Silicon ASSEMBLY RELATED INFORMATION: Substrate Potential: Unbiased (DI) ADDITIONAL INFORMATION: Worst Case Current Density 7 A/cm HS-82C54RH (21) CS (20) A1 (19) A0 (18) CLK 2 (17) OUT 2 (16) GATE 2 ...
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... For information regarding Intersil Corporation and its products, see web site www.intersil.com Sales Office Headquarters NORTH AMERICA Intersil Corporation P. O. Box 883, Mail Stop 53-204 Melbourne, FL 32902 TEL: (321) 724-7000 FAX: (321) 724-7240 17 HS-82C54RH EUROPE Intersil SA Mercure Center 100, Rue de la Fusee 1130 Brussels, Belgium TEL: (32) 2.724.2111 FAX: (32) 2.724.22.05 ASIA Intersil Ltd ...