ml7055 Oki Semiconductor, ml7055 Datasheet - Page 22

• Manufacturer Part Number: ml7055
• Description: Bluetooth Baseband Controller Ic
• Manufacturer: Oki Semiconductor

APPLICATION NOTES
Clock Selection
Setting the Reset
Setting the UART Baud Rate
Setting the PCM-CVSD Transcoder
OKI Semiconductor
x The system clock frequency is selected according to external pin SFRQSEL.
x The CPU clock supply source is selected according to external pin SCLKSEL.
x The frequency of CPU clock is selectable from the high speed (24 MHz) and low speed (16 MHz). This
x Apply a “L” level to the RESET pin for more than 10 Ps after power voltage is stabilized. When the
x It is possible to set the UART baud rate using the Vendor Specific Commands.
x It is possible to set the PCM-CVSD transcoders using the Vendor Specific Commands.
x It is possible to set the following parameters using the VCCTL command:
can be performed by the Vendor Specific Command.
SFRQSEL = 0 :
SFRQSEL = 1 :
SCLKSEL = 0 :
SCLKSEL = 1 :
Note: The clock supply source can be set by the CLKCNTL register in the CTL/WDT block once the
system clock oscillator circuit is stable and the RESET pin is at a “H” level, the internal reset is released
and operation starts after the internal reset is held for 1.9 ms for the input clock of 13 MHz or 2.0 ms for
the input clock of 12 MHz.
Available baud rate settings:
9600/19.2k/38.4k/56k/57.6k/115.2k/230.4k/345.6k/460.8k/921.6k
(Initial value is 115.2 kbps.)
For command details, contact Oki Electric Industry Co., Ltd.
- PCMSYNC/PCMCLK mode (initial setting: input)
- Mute reception (initial setting: OFF)
- Mute transmission (initial setting: OFF)
- Air coding
- Interface coding
- PCM format (data width of one PCM Linear sample)
- Serial interface format
8-bit (initial setting)/14-bit/16-bit
CVSD (initial setting)/P-law/A-law
Linear (initial setting)/P-law/A-law
Short frame (initial setting)/long frame
LSI is powered up.
A 13 MHz clock is input to external pins SCLKP.
A 12 MHz clock is input to external pins SCLKP.
Use the clock that was divided down from the internal PLL output of 192 MHz that
was generated from external pins SCLKP. (Dividing ratios are selectable in the
range of 1/6 to 1/16. Initial value is 1/8 (24 MHz).)
Use external pins XC32KP.
FEDL7055-02
ML7055
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