ml7074-003 Oki Semiconductor, ml7074-003 Datasheet - Page 37

• Manufacturer Part Number: ml7074-003
• Description: Dual Echo Canceler & Noise Canceler With Dual Codec For Hands-free Msm7731-02dual Echo Canceler & Noise Canceler With Dual Codec For Hands-free
• Manufacturer: Oki Semiconductor

(11) CR10 (Echo canceler I/O level setting)
B7, 6
B5, 4
B3, 2
B1, 0
OKI Semiconductor
Initial Value
CR10
Acoustic output level control
Acoustic input level control
Line output level control
Line input level control
These bits control the PAD level of the gain of the acoustic echo canceler’s SoutA output. PAD is turned
ON or OFF by either the GLPADTHR pin or the GLPADTHR control register bit (CR1-B2). It is
recommended to set the level to the positive level equal to LPADA2 and LPADA1. If the pin setting is
changed, the coefficient reset must be activated by either the RST pin or the RST bit (CR0-B6). Because
these bits are read in synchronization with the rising edge of the SYNC signal, hold the data in these bits
for 250 µs or longer.
These bits control the PAD level of the loss of the acoustic echo canceler’s SinA input. PAD is turned
ON or OFF by either the GLPADTHR pin or the GLPADTHR control register bit (CR1-B2). Set the
level so that echo return loss (value of returned echo) will be attenuated. If the pin setting is changed, the
coefficient reset must be activated by either the RST pin or the RST bit (CR0-B6). Because these bits
are read in synchronization with the rising edge of the SYNC signal, hold the data in these bits for 250
µs or longer.
These bits control the PAD level of the loss of the line echo canceler’s SoutL output. PAD is turned ON
or OFF by either the GLPADTHR pin or the GLPADTHR control register bit (CR1-B2). It is
recommended to set the level to the positive level equal to LPADL2 and LPADL1. If the pin setting is
changed, the coefficient reset must be activated by either the RST pin or the RST bit (CR0-B6). Because
these bits are read in synchronization with the rising edge of the SYNC signal, hold the data in these bits
for 250 µs or longer.
These bits control the PAD level of the loss of the line echo canceler’s SinL output. PAD is turned ON
or OFF by either the GLPADTHR pin or the GLPADTHR control register bit (CR1-B2). Set the level
so that echo return loss (value of returned echo) will be attenuated. If the pin setting is changed, the
coefficient reset must be activated by either the RST pin or the RST bit (CR0-B6). Because these bits
are read in synchronization with the rising edge of the SYNC signal, hold the data in these bits for 250
µs or longer
GPADA2
B7
0
(0, 1):
(0, 0):
(1, 1):
(1, 0):
(0, 1):
(0, 0):
(1, 1):
(1, 0):
(0, 1):
(0, 0):
(1, 1):
(1, 0):
(0, 1):
(0, 0):
(1, 1):
(1, 0):
GPADA1
B6
+ 18 dB
+ 12 dB
+ 6 dB
– 18 dB
– 12 dB
– 6 dB
+ 18 dB
+ 12 dB
+ 6 dB
– 18 dB
– 12 dB
– 6 dB
0
0 dB
0 dB
0 dB
0 dB
LPADA2
B5
0
LPADA1
B4
0
GPADL2
B3
0
GPADL1
B2
0
LPADL2
B1
0
FEDL7731-02-11
MSM7731-02
LPADL1
B0
0
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