msm7582 Oki Semiconductor, msm7582 Datasheet - Page 17

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msm7582

Manufacturer Part Number
msm7582
Description
P/4 Shift Qpsk Modem
Manufacturer
Oki Semiconductor
Datasheet

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FUNCTIONAL DESCRIPTION
Control Registers
(1) CR0 (basic operation mode setting)
* the initial value is set when a reset signal is supplied by a PDN.
B7: PS/CS selection
B6: Transmit timing clock selection
B5: Modulation on/off control
B4, B3: Receiver input IF frequency selection
B2: Transmit envelope (I
B1, B0: Test mode selection bits. Each monitor output is output to the transmit ENV pin.
CR0
Initial value (*)
1/CS (4 Clock recovery DPLLs are on.)
0/PS (2 Clock recovery DPLLs are on.)
0/TXCI input: 384 kHz.
TXCO output: 384 kHz output from APLL. Transmit data TXD is input in synchronization
1/TXCI input: 3.84 MHz.
TXCO output: 384 kHz (one-tenth of the TXCI frequency). Transmit data TXD is input in
1/modulation OFF (with phase fixed)
0/modulation ON.
(0, 0), (0, 1):
(1, 0):
(1, 1):
1/I
0/
(0, 0): Transmit envelope (I
(0, 1): receiver phase detection signal output
(1, 0): receiver delay detection signal output
(1, 1): receiver AFC information output
2
I
+ Q
2
+ Q
2
2
output
output
PS/CS
with the rising edge of TXCI (APLL is on.)
synchronization with the rising edge of TXCO (APLL is off.)
1.2 MHz
10.8 MHz
10.7 MHz/10.75 MHz
B7
0
2
+ Q
TXC SEL
2
B6
0
2
or
+ Q
I
2
2
+ Q
MOD OFF
or
B5
0
2
I
)output selection
2
+ Q
2
IFSEL 1
) output
B4
0
IFSEL 0
B3
0
ENV SEL
B2
0
MSM7582/7582B
TEST 1
B1
0
TEST 0
17/24
B0
0

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