msm7581 Oki Semiconductor, msm7581 Datasheet - Page 12

• Manufacturer Part Number: msm7581
• Description: Itu-t G.721 4ch Adpcm Transcoder
• Manufacturer: Oki Semiconductor

Internal Latch timing (A)
THR Processing Timing
Timing Block Diagrams, when CODER and DECODER output data, are shown in the following
figures.
The parallel to serial conversion of the output unit employs a load format and the load point is
at the rising edge of a synchronous signal.
Therefore, input THR signal with respect to SYXA for CODER with timing of satisfying ts and
th conditions shown in the figure.
For DECODER, THR signal should be input even of through-data is input.
The input timing should satisfy the conditions shown in the following figures.
CODER
Note: That data-ship may occur when the rising edge (data load point) of SYXA and input of
ADPCM side SYNC (SYXA)
¡ Semiconductor
Through-data Output (SOA)
Internal Input Data
PCM side SYNC (SYXP)
PCM Input (SIP)
BCKA
THR
SYXP
SIP
BCKP
THR
the internal latch timing overlap each other.
Parallel
Serial
MSB
8
Latch timing=A
Latch
Through-data
ADPCM
CODER
8b
LSB
4b
Through-data
ts
S
E
L
th
MSB
Parallel
Serial
ts=100ns or more
th=100ns or more
MSM7581
SYNCA
SOA
BCLKA
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