msm7730 Oki Semiconductor, msm7730 Datasheet - Page 14

• Manufacturer Part Number: msm7730
• Description: Wireless Lan Baseband Controller
• Manufacturer: Oki Semiconductor

Shared RAM Interface Signal Descriptions
EEPROM Interface Signal Descriptions
Radio Interface Signal Descriptions
12
RA[16:0]
RD[15:0]
RCELN
RCEHN
RWRN
EEDIO
EECS
EESK
RXC1
TXC, TXC2
RADPWR
ANT
SLICE
SYNCLK,
SYNDAT,
SYNLEN
LKDET
MSM7730
Pin Name
Pin Name
Pin Name
Oki Semiconductor
–––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––
Output
Bidirectional
Output
Output
Output
Bidirectional
Output
Output
Open-
collector/drain
Output
Open-
collector/drain
Output
Open-
collector/drain
output
Open-collector
output
Open-
collector/drain
output
Open collector
Input
Direction
Direction
Direction
The RAM address is provided by these pins. A maximum address size of 128K words is supported.
The RAM data is provided on these pins. Word or byte operations are supported. When the shared memory is
not in use, the data bus is output to prevent a floating data bus consuming power.
When asserted, a low byte (or word) shared RAM cycle is active.
When asserted, a high byte (or word) shared RAM cycle is active.
When asserted, a write cycle is required. When deasserted a read cycle is required. This signal remains valid
before and while RCELN and RCEHN are asserted.
This is a bidirectional data signal for the EEPROM connected directly to data in (DI) of the EEPROM, and to data
out (DO) via a resistor (see EEPROM application notes and Figure 2 ).
This signal is connected to CS of the EEPROM to provide the chip select.
This signal is connected to SK of the EEPROM to provide the clock. The clock rate is RCK divided by 64 (250
kHz with RCK at 16 MHz).
When asserted reception is enabled, RXC1 is always asserted during reception. This signal is programmable
to be open-collector (active low) or open-drain (active high).
When asserted transmission is enabled, both signals are programmable to be open-collector (active low) or
open-drain (active high). Transmit is only activated following a receive (where Clear Channel Assessment is
performed). The timing of TXC1 and TXC2 at the start of a transmit is programmable from the deassertion of
RXC1. RXC2 is typically used for TX Power Amplifier switching, and its assertion depends on the power control
mode selected in the MSM7730.
This pin is asserted to power up the radio circuitry (i.e.,local oscillators) for reception. The pin is programmable
to be open-collector (active low) or open-drain (active high).
This pin selects one of two antennas for transmission or reception.
This control pin determines the response time constant of an analog data slicer when using the internal modem
with an analog data slicer circuit (options MSEL-0 or 1). This pin is programmable to be open-collector (active
low) or open-drain (active high). The pin is asserted when CCA has determined a valid IEEE 802.11 GH signal
(preamble is detected).
These signals provide the interface to the radio synthesizer to select the transmit/receive carrier. Many
synthesizers are supported by a flexible architecture. The data is output on SYNDAT ready for the rising edge
of SYNCLK. SYNLEN is asserted during the programming, and the data is latched on the rising edge of
SYNCLEN. SYNCLK is clocked at RCK divided by 2.
SYNCLK and SYNDAT also are used to program a serial DAC used for TX power control, CCA threshold and
RSSI measurement (see below). The synthesizer is programmed when the radio is idle. The RSSI and CCA
threshold DAC is used at the start of receiving a packet. The TX power DAC is programmed at the start of
transmitting packet.
The radio provides indication of being in lock with LKDET. This input is active high or low (programmable),
pulse sensitive, and latched so that both pulsed and steady out-of-lock signals are recognized. Glitches shorter
than 2 RCK periods are ignored. Transmission is prevented when the synthesizer is out-of-lock
Description
Description
Description