msm7620 Oki Semiconductor, msm7620 Datasheet - Page 8

• Manufacturer Part Number: msm7620
• Description: Echo Canceler
• Manufacturer: Oki Semiconductor

¡ Semiconductor
(4/5)
32-pin
SSOP
24
25
27
28
29
Pin
64-pin
QFP
40
41
44
45
46
Symbol
SYNCO
SCKO
WDT
RST
GC
Type
O
O
O
I
I
8 kHz sync signal for the PCM CODEC.
Connect this pin to the SYNC pin and the PCM CODEC transmit/receive
sync pin.
Leave it open if using an external SYNC.
Input signal for the gain controller when RIN input is controlled and the
RIN input level is controlled and howling is prevented.
The gain controller adjusts the RIN input level when it is –20 dBm0 or
above. RIN input levels from –20 to –11.5 dBm0 will be suppressed to
–20 dBm0 in the attenuation range from 0 to 8.5 dB.
RIN input levels above –11.5 dBm0 will always be attenuated by 8.5 dB.
• Single Chip or Master Chip in a Cascade Connection
This pin is loaded in synchronization with the falling edge of the INT
signal or the rising edge of RST.
Transmit clock signal (200 kHz) for the PCM CODEC.
Connect this pin to the SCK pin and the PCM CODEC transmit/receive
clock pin.
Not affected by reset. Outputs "0" during power-down.
Leave it open if using an external SCK.
Reset signal.
During initialization, input signals, except for PWDWN are disabled for
100 ms after reset (after RST is returned from "L" to "H").
Input the basic clock during the reset.
Output pins during reset are in the following sates :
Test pin.
Leave this pin open.
• Slave Chip in a Cascade Connection
"L": Reset mode
"H": Normal operation mode
"H": Gain control ON
"L": Gain control OFF
"H" is recommended for echo cancellation.
Fixed at "L"
High impedance: SOUT, ROUT, PD0 to 15
"L": WDT
"H": OF1, OF2
Not affected: X2, SYNCO, SCKO, IRLD, MCKO
Description
MSM7620
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