ml87v5002 Oki Semiconductor, ml87v5002 Datasheet - Page 25

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ml87v5002

Manufacturer Part Number
ml87v5002
Description
Audio Delay Ic With Built-in 2-mbit Dram
Manufacturer
Oki Semiconductor
Datasheet
OKI Semiconductor
DRAM refresh interval setting
Register Name
Register Name
Default Value
REF_ITVL
DATA_BIT
512FS
384FS
256FS
192FS
512FS
384FS
256FS
192FS
128Fs
128Fs
[5:0]
WR
RD
Table 23 Descriptions of DRAM Refresh Interval Setting Register Functions
01_1101 (29)
01_0110 (22)
00_1110 (14)
00_1011 (11)
00_0111 (07)
122.070 ns
162.760 ns
244.141 ns
61.035 ns
81.380 ns
(14.16
(14.32
(13.67
(14.32
(13.67
Specifies the DRAM refresh interval.
The refresh interval is 8 x SYSCLK x REF_ITVL.
The value (refresh interval) should be set around 14 µs (15.6µs x 0.9) by this register.
32kHz
32kHz
BIT7
Table 22
Table 24 Examples of REF_ITVL Setting by SYSCLK
0
µ
µ
µ
µ
µ
s)
s)
s)
s)
s)
Table 25 SYSCLK Cycle by SYSCLK Input
DRAM Refresh Interval Setting Register Map
BIT6
SUB_ADDRESS=05h(R/W)
0
10_1000 (40)
01_1110 (30)
01_0100 (20)
00_1111 (15)
00_1010 (10)
118.103 ns
177.154 ns
44.289 ns
59.051 ns
88.577 ns
(14.17
(14.17
(14.17
(14.17
(14.17
44.1kHz
44.1kHz
µ
µ
µ
µ
µ
BIT5
Description
s)
s)
s)
s)
s)
V
V
0
BIT4
10_1011 (43)
10_0000 (32)
01_0110 (22)
01_0000 (16)
00_1011 (11)
122.070 ns
162.760 ns
40.690 ns
54.253 ns
81.380 ns
V
V
1
(13.99
(13.88
(14.32
(13.88
(14.32
48kHz
48kHz
µ
µ
µ
µ
µ
s)
s)
s)
s)
s)
BIT3
V
V
0
REF_ITVL
10_1011 (43)
10_0000 (32)
01_0110 (22)
40.690 ns
54.253 ns
81.380 ns
(13.99
(13.88
(14.32
BIT2
96kHz
96kHz
V
V
1
--
--
--
--
µ
µ
µ
s)
s)
s)
BIT1
V
V
1
10_1011 (43)
40.690 ns
FEDL87V5002-01
(13.99
192kHz
192kHz
ML87V5002
--
--
--
--
--
--
--
--
BIT0
µ
V
V
0
s)
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