ml86v7667 Oki Semiconductor, ml86v7667 Datasheet
ml86v7667
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ml86v7667 Summary of contents
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... USES AND APPLICATION EXAMPLES The ML86V7667 can be used as a video signal input interface IC in any system carrying out digital image processing. It can be operated using digital PLL with line-locked clock in applications requiring high picture quality. Also, high-speed synchronous operation using asynchronous clock is possible in applications requiring high-speed synchronization, such as switching operation using multichannel inputs ...
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... Output pixel count correction function using built-in FIFO FIFO Mode/FIFO through mode selectable Automatic switching between FIFO and FIFO through modes Sleep mode Hi-impedance mode for output pins Other Sections 2 I C-bus interface Single 3.3 V power supply (5 V tolerant input) Package: 64-pin plastic TQFP (TQFP64-P-1010-0.50-K) PEDL86V7667-00 ML86V7667 2 C 2/31 ...
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... OKI Semiconductor BLOCK DIAGRAM PLL Analog Block Vin1 10-bit ADC Vin2 Test Control SYNC Block Y/C C Chroma Separation Block 2-line or 3-line Adaptive Y Luma Comb Block VBID Detection Block Block I2C-BUS Control Block PEDL86V7667-00 ML86V7667 VSYNC_L HSYNC_L HVALID VVALID YCbCr [7:0] STATUS1 STATUS2 STATUS3 STATUS4 3/31 ...
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... GAINS[ GAINS[ INS 6 1 ADOFF 6 2 DGND 6 3 PLL DVDD 6 4 64-Pin Plastic TQFP (TQFP64-P-1010-0.50-K) DIGITAL DIGITAL ANALOG PEDL86V7667-00 ML86V7667 DVDD 3 2 DGND 3 1 STATUS4 3 0 STATUS3 STATUS2 STATUS1 2 7 SCL 2 6 SDA 2 5 TEST[ ...
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... STATUS output pin 1. Selected by the internal register. Default HVALID O STATUS output pin 2. Selected by the internal register. Default VVALID O STATUS output pin 3. Selected by the internal register. Default ODD/EVEN O STATUS output pin 4. Selected by the internal register. Default CSYNC PEDL86V7667-00 ML86V7667 Should be left pen. Should be left pen. Should be left pen. 5/31 ...
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... Reference clock for PLL (Pin 47 = “1”) Register $20/PLLR1[ MHz 1: 25 MHz I2C bus slave address selection. Put this pin into the “0” state I when not used. 0: 1000 001X ( Write 1 = Read) 1: 1000 011X ( Write 1 = Read) PEDL86V7667-00 ML86V7667 6/31 ...
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... External setting pin for input pin switching. Put this pin into the “0” I state when not used. Valid when external pin 53 M[1] = “0”. INS Input pin [0] VIN1(pin 8) Composite-1 [1] VIN2(pin 9) Composite-2 ADC stop signal. Normally set to “0”. I Digital ground. Digital power supply. PEDL86V7667-00 ML86V7667 7/31 ...
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... Internal register analog gain setting mode Analog Input Requirements Control pin Register Pin 53 M[ Pin 53 M[ INS ADC1[0] VIN1 [0] *[0] Composite [1] [1] Pin 53 M[ Setting gain value Register Typical value (X times) $1F/ADC2[6:4] [000] *[001] [010] [011] [100] [101] [110] [111] PEDL86V7667-00 ML86V7667 Input pin VIN2 Composite 0.55 0.70 0.93 1.21 1.60 2.09 2.65 3.45 8/31 ...
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... Signals of the following special standards other than normal NTSC/PAL signals can be decoded. # Related register $00/MRA[2:1] MRA[2:1] = "00" Normal mode MRA[2:1] = "01" NTSC443 MRA[2:1] = "10" PAL M, N MRA[2:1] = "11" Setting prohibited PEDL86V7667-00 ML86V7667 PAL Y/C separation 2-line comb/trap adaptive transition filter 2-line comb filter Trap filter Undefined Undefined ...
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... Aper tur e bandpass filter, cor ing filter for contour compensation, and luminance pr e-filter Adjustment is performed by combining the following registers. Aperture bandpass filter coefficient setting: # Related register $OC/LUMC[6:5] Coring range setting: # Related register $OC/LUMC[4:3] Aperture weighting factor setting: # Related register $OC/LUMC[2:0] PEDL86V7667-00 ML86V7667 10/31 ...
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... The FIFO-2 mode is more effective than the FIFO-1 mode for non-standard signals. MRD[7:6] = "10" : FIFO through mode This is the mode in which the value of the decoded result of an input signal is output without correcting the pixel count by the internal FIFO. MRD[7:6] = "11" : Undefined PEDL86V7667-00 ML86V7667 11/31 ...
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... Control pin Register (Pin 57) MODE[2] MRA[7:6] [0] [1] *[01] Input Clock Settings Input clock PLL reference clock PLLR1[6]=0 PLLR1[6]=1 32MHz 25MHz Sampling clock input according to — — the operating mode (See the table on the next page.) PEDL86V7667-00 ML86V7667 Register MRC[5] [00 Asynchronous clock — 12/31 ...
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... Related registers: $2B/AIREG, $2C/STATUS, $2D/VFLAG $00/MRA[0]=0 * $00/MRA[0]=1 Control pin Register (Pins 55, 56) MODE[1:0] $00/MRA[5:3] [00] *[000] [01] [001] — [010] — [011] [10] [100] [11] [101] — [110] — [111] PEDL86V7667-00 ML86V7667 Sampling clock (double-speed) Pin 51 CLKX2 27 MHz 24.545454 MHz 28.63636 MHz — 27 MHz 29.5 MHz — — 13/31 ...
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... For more information, contact the Phillips Corporation. Test Contr ol Block This block is used to test the LSI chip not intended for user use standard of the Phillips Corporation. The registers patent is required to use control, but if this I PEDL86V7667-00 ML86V7667 2 C bus. 2 C-bus is used to 14/31 ...
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... Condition Min. — 2.2 — 0.8VDD — 0 Ioh = 2 mA (*4) 0.7VDD Ioh = 4 mA (*5) Iol = 2 mA (*4) 0 Iol = GND to VDD GND to VDD 10 C 0.4 Coupling PEDL86V7667-00 ML86V7667 Rating Unit –0.3 to +4.5 V –0 –55 to +150 °C Typ. Max. Unit 3.3 3.6 V — 1.1 Vp-p — ...
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... MHz 50 24.545454 MHz 25 27 MHz 25 28.63636 MHz 25 29.5 MHz 25 24.545454 MHz 40 27 MHz 45 28.63636 MHz 45 29.5 MHz 50 24.545454 MHz 25 27 MHz 25 28.63636 MHz 25 29.5 MHz 25 0 PEDL86V7667-00 ML86V7667 Max. Unit VDD=3. ...
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... CLKSEL CLKSEL CLKSEL CLKSEL CLKSEL CLKSEL CLKSEL CLKSEL: L 200 Pull up = 4.7k 100 Pull up = 4.7k 200 PEDL86V7667-00 ML86V7667 Typ. Max. Unit — 27.0 MHz — MHz — MHz — 29.5 MHz — ppm 100 — — — ...
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... STATUS[4:1] Reset Timing OFF POWER ON See clock oscillator’s data sheet. GND CLKX2 RESET_L (*) Output data is “don’t care” at reset. Tclkx2 tr tcxd22 tcxd22 Tod21 Tod2x21 Tod22 Tod2x22 Tod23 Tod2x23 VDD Set up Time rst_w Don’t Care PEDL86V7667-00 ML86V7667 tf Valid Clock 18/31 ...
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... Stop condition setup time 2 The I C-bus timing should be designed based on the table above ACK t C_SCL tF tHD:STA S tHIGH tSU:DAT tSU:STA Min. Typ. 0 100 4.7 4.0 4.7 4.0 4.7 300 250 4.7 PEDL86V7667-00 ML86V7667 ACK 3-8 Stop Condition P tSU:STO Max. Unit 400 KHz 300 ns s 19/31 ...
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... Vertical Sync Signals (60 Hz) 624 625 312 313 314 315 316 317 318 Vertical Sync Signals (50 Hz) PEDL86V7667-00 ML86V7667 283 284 285 319 336 337 338 20/31 ...
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... In the FIFO mode, the output cycle is fixed, so the delay varies. In the PAL mode, where Y/C separation is performed by trap filter not added. Data delay Blank HSYNC delay Absorption difference Pixel rate, Input signal FIFO/FM mode Composite FIFO-1 Composite FM Composite FIFO-1 Composite FM PEDL86V7667-00 ML86V7667 Active Data = FIFO Delay 1.5H 1.5H 1.5H 1.5H 21/31 ...
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... PEDL86V7667-00 ML86V7667 60 pixels Total lines (VSYNC_L) Active lines (VVALID) V Total Active Total V blank lines lines 858 Odd/20 Odd/243 Odd/263 780 Even/20 Even/242 Even/262 910 864 ...
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... Each VALID signal and the ODD/EVEN signal are selected by the STATUS signal. VSYNC_L, ODD/EVEN HSYNC_L VSYNC_L 1 pixel ODD/EVEN ODD (STATUS) VSYNC_L ODD/EVEN (STATUS) VALID Signal HSYNC_L 60 pixels Back Front HVALID porch porch 2 pixels VVALID 60pixels 1 pixel EVEN PEDL86V7667-00 ML86V7667 0 pixel 23/31 ...
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... OKI Semiconductor Output Timing by Mode 8-bit Y/CbCr Multiplexed Output CLKX2O CLKXO HVALID Y[7:0] Cr-2 Y-1 Cb0 Y0 Crn-3 Yn-2 Cbn-1 Yn-1 Crn-1 Yn Cr0 Y1 Cb2 Y2 Cr2 PEDL86V7667-00 ML86V7667 Cbn+1 24/31 ...
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... Video data block 1440T(PAL/NTSC) Multiplexed video data Cb0 Y0 Cr0 Y1 Cb2 Y2 Cr2 Y3 Cb4 Y4 ------- Cr718 Y719 4T Digital line Total pixels Active pixels SAV: Start of active video timing reference code EAV: End of active video timing reference code T: clock periods 37ns normal (1/27MHz) PEDL86V7667-00 ML86V7667 60 pixels 25/31 ...
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... PEDL86V7667-00 ML86V7667 HEX LSB [1] [ ...
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... Default Value [7] [6] [5] [4] [ PEDL86V7667-00 ML86V7667 HEX LSB [2] [1] [ 27/31 ...
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... Before using the decoder, please carefully evaluate and consider the signal conditions and usage environment of the intended use. In addition to this Data Sheet, a ML86V7667 User's Manual is also available. The User's Manual explains each register and provides examples of adapted circuits as well as other information helpful in the design phase. Please read the User's Manual before embarking on design work ...
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... The surface mount type packages are very susceptible to heat in reflow mounting and humidity absorbed in storage. Therefore, before you perform reflow mounting, contact Oki’s responsible sales person for the product name, package name, pin number, package code and desired mounting conditions (reflow method, temperature and times). PEDL86V7667-00 ML86V7667 (Unit: mm) 29/31 ...
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... OKI Semiconductor REVISION HISTORY Document No. Date PEDL86V7667-00 Oct. 20, 2004 Page Previous Current Edition Edition – – Preliminary edition 1 PEDL86V7667-00 ML86V7667 Description 30/31 ...
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... The purchaser assumes the responsibility of determining the legality of export of these products and will take appropriate and necessary steps at their own expense for these part of the contents contained herein may be reprinted or reproduced without our prior permission. PEDL86V7667-00 ML86V7667 Copyright 2005 Oki Electric Industry Co., Ltd. 31/31 ...