ml86v7668a Oki Semiconductor, ml86v7668a Datasheet - Page 12

• Manufacturer Part Number: ml86v7668a
• Description: Ntsc/pal/secam Digital Video Decoder
• Manufacturer: Oki Semiconductor

Synchronization Block
This block controls the sync signals for internal operation, output sync signals, and the timing for each block.
Synchronization detection levels, output timing, and various other functions can be adjusted by the registers listed
below.
·
OKI Semiconductor
PLL Function
The digital PLL circuit generates an operating clock synchronized with the horizontal sync signals of the video
signals. With the input of a 25 MHz or 32 MHz reference clock, the double-speed pixel clock for each mode is
provided as a line lock clock and used as the sampling clock.
The asynchronous sampling mode, which uses a fixed clock directly, can be used without using PLL.
# Related registers: $70/PLLC1, $71/PLLC2, $72/PLLC3, $73/PLLC4
In the PLL mode, a double-speed line lock clock is generated by setting the operating mode.
*: Default
NTSC Square pixel
Pin 44 PLLSEL
Operating mode
12.272727 MHz
ITU-R BT.601
PLLSEL = “0”
PLLSEL = “1”
Fixed clock
Control pin
PLL clock
13.5 MHz
$70/PLLC1[6] = “0” *
$01/IOC2[0] = “0” *
Input the sampling clock according to the
Operating Modes/Sampling Clock Settings
Control pin
MODE[0]
32 MHz
(Pin 33)
0
1
(See the table below)
operating mode.
Input Clock Settings
Input clock
$70/PLLC1[6] = “1”
$01/IOC2[0] = “1”
$00/IOC1[1]
Register
25 MHz
0 *
1
Sampling clock (double-speed)
$70/PLLC1[7] = “0” *
$70/PLLC1[7] = “1”
Fixed PLL clock
24.545454 MHz
Pin 46 CLKX2
Asynchronous
Sampling
Line lock
27 MHz
FEDL86V7668A-01
ML86V7668A
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