nw6005 Integrated Device Technology, nw6005 Datasheet - Page 2

• Manufacturer Part Number: nw6005
• Description: Enhanced Type Ii Caller Id Decoder
• Manufacturer: Integrated Device Technology

PIN INFORMATION
NW6005 ENHANCED TYPE II CALLER ID DECODER
OSCOUT
Name
OSCIN
DCLK
DATA
VREF
IN1+
GND
GS1
CB0
IN1-
Type
I/NC
O
O
O
O
I
I
-
I
I
Pin No.
10
1
2
3
4
5
6
7
8
9
Reference Voltage.
This output is used to bias the input OP amp. It is typically VCC/2.
Non-inverting Input of the gain adjustable Tip/Ring OP amp.
Inverting Input of the gain adjustable Tip/Ring OP amp.
Gain Select Output of the gain adjustable Tip/Ring OP amp.
The Tip/Ring signal can be attenuated or amplified at GS1 by adjusting the feedback resistor between GS1 and
IN1-. The FSK signal is always detected by Tip/Ring OP amp while DT-AS signal can be detected by either
Tip/Ring or Hybrid OP amp. The OP amp selection is controlled by CB1 and CB2 pins.
Ground.
Oscillator Input.
A 3.579545 MHz crystal or ceramic resonator should be connected between this pin and the OSCOUT. It can also
be driven by an external clock source.
Oscillator Output.
A 3.579545 MHz crystal or ceramic resonator should be connected between this pin and the OSCIN. When an
external clock drives OSCIN, this pin can be left floating.
Control Bit 0 (FSK Data Interface Mode Select).
This pin can select the 3-wire FSK data interface mode. A ‘0’ on this pin indicates interface mode 0; while a ‘1’ on
this pin indicates interface mode 1. (The FSK data interface is consisted of DATA, DCLK and DR/STD pins.)
When CB0 is high and CB1, CB2 are both low, the device is set into the power down state.
Data Clock of the Serial FSK Interface.
In mode 0 (CB0 is low), this pin is unused; In mode 1 (CB0 is high), this pin is an input which clock the FSK data
byte out to the DATA pin.
Data Output of the Serial FSK Interface.
In mode 0 (CB0 is low), the FSK serial bit stream is output to the DATA pin directly.
In mode 1 (CB0 is high), the start bit is stripped off, the data byte and the stop bit is stored in a 9-bit buffer. At the
end of each word signaled by the DR/STD pin, the microcontroller should shift the byte out onto the DATA pin by
applying 8 read pulses to the DCLK pin. A 9
OSCOUT
OSCIN
DCLK
DATA
VREF
GND
IN1+
GS1
CB0
IN1-
Figure 2. Pin Assignment
1
2
3
4
5
6
7
8
9
10
2
th
DCLK pulse will shift out the stop bit for framing error checking.
20
19
18
17
16
15
14
13
12
11
Description
IN2+
IN2-
GS2
CB2
CB1
VCC
CD
ST/GT
EST
DR/STD
INDUSTRIAL TEMPERATURE RANGE