92hd88b4x5ndg Integrated Device Technology, 92hd88b4x5ndg Datasheet - Page 70
92hd88b4x5ndg
Manufacturer Part Number
92hd88b4x5ndg
Description
Single Chip Pc Audio System Codec+mono Speaker Amplifier+capless Hp+ldo
Manufacturer
Integrated Device Technology
Datasheet
1.92HD88B4X5NDG.pdf
(277 pages)
- Current page: 70 of 277
- Download datasheet (4Mb)
IDT PROPRIETARY / IDT
SINGLE CHIP PC AUDIO SYSTEM, CODEC+SPEAKER AMPLIFIER+CAPLESS HP+LDO
92HD88
SINGLE CHIP PC AUDIO SYSTEM, CODEC+SPEAKER AMPLIFIER+CAPLESS HP+LDO
Field Name
Rsvd
Data2
Data1
Data0
Field Name
Rsvd
Mask2
Mask1
Reg
Get
Set
8.3.12. AFG (NID = 01h): GPIOEn
Byte 4 (Bits 31:24)
CONFIDENTIAL
Bits
31:3
Reserved.
2
Data for GPIO2. If this GPIO bit is configured as Sticky (edge-sensitive) input,
it can be cleared by writing "0". For details of read back value, refer to HD Audio
spec. section 7.3.3.22
1
Data for GPIO1. If this GPIO bit is configured as Sticky (edge-sensitive) input,
it can be cleared by writing "0". For details of read back value, refer to HD Audio
spec. section 7.3.3.22
0
Data for GPIO0. If this GPIO bit is configured as Sticky (edge-sensitive) input,
it can be cleared by writing "0". For details of read back value, refer to HD Audio
spec. section 7.3.3.22
Bits
31:3
Reserved.
2
Enable for GPIO2: 0 = pin is disabled (Hi-Z state); 1 = pin is enabled; behavior
determined by GPIO Direction control
1
Enable for GPIO1: 0 = pin is disabled (Hi-Z state); 1 = pin is enabled; behavior
determined by GPIO Direction control
Byte 3 (Bits 23:16)
R/W
R
RW
RW
RW
R/W
R
RW
RW
F1600h
Default
00000000h
0h
0h
0h
Default
00000000h
0h
0h
70
Byte 2 (Bits 15:8)
Reset
N/A (Hard-coded)
POR - DAFG - ULR
POR - DAFG - ULR
POR - DAFG - ULR
Reset
N/A (Hard-coded)
POR - DAFG - ULR
POR - DAFG - ULR
92HD88
Byte 1 (Bits 7:0)
716h
PC AUDIO
V 0.94 07/11
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