zl30111 Zarlink Semiconductor, zl30111 Datasheet
zl30111
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zl30111 Summary of contents
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... Rate convert NTR 8kHz or GPON physical interface clock to TDM clock Description The ZL30111 POTS line card PLL contains a digital phase-locked loop (DPLL), which provides timing and synchronization for SLIC/CODEC devices. The ZL30111 generates TDM clock and framing signals that are phase locked to the input reference. ...
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... Normal Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 4.0 Measures of Performance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 4.1 Jitter 4.2 Jitter Generation (Intrinsic Jitter 4.3 Jitter Transfer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 4.4 Lock Time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 5.0 Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 5.1 Power Supply Decoupling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 5.2 Master Clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 5.2.1 Clock Oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 5.2.2 Crystal Oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 5.3 Power Up Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 5.4 Reset Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 6.0 Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 6.1 AC and DC Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 6.2 Performance Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 ZL30111 Table of Contents 2 Zarlink Semiconductor Inc. Data Sheet ...
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... Figure 2 - Pin Connections (64 pin TQFP, please see Note Figure 3 - Reference Monitor Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Figure 4 - DPLL Mode Switching . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Figure 5 - Clock Oscillator Circuit Figure 6 - Power-Up Reset Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Figure 7 - Timing Parameter Measurement Voltage Levels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Figure 8 - Input to Output Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Figure 9 - Output Timing Referenced to F8o . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 ZL30111 List of Figures 3 Zarlink Semiconductor Inc. Data Sheet ...
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... Figure 2 - Pin Connections (64 pin TQFP, please see Note 1) Note 1: The ZL30111 uses the TQFP shown in the package outline designated with the suffix QD, the ZL30111 does not use the e-Pad TQFP. ZL30111 ZL30111 2 4 ...
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... OSCo. For clock oscillator operation, this pin must be connected to a clock source Internal Connection. Leave unconnected. 23 GND Ground internal bonding Connection. Leave unconnected Positive Supply Voltage. +3 Internal Connection. Connect this pin to GND. ZL30111 Description nominal. DC nominal. DC nominal. DC nominal Zarlink Semiconductor Inc. Data Sheet ...
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... Frame Pulse ST-BUS 2.048 Mbps (Output). This output kHz 244 ns active low framing pulse, which marks the beginning of an ST-BUS frame. This is typically used for ST-BUS operation at 2.048 Mbps and 4.096 Mbps Internal Connection. Leave unconnected. 51 AGND Analog Ground ZL30111 Description nominal. DC nominal. DC nominal. DC nominal. ...
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... IC Internal Connection. Connect this pin to VDD Positive Supply Voltage. +3 internal bonding Connection. Leave unconnected Internal Connection. Connect this pin to GND Internal Connection. Connect this pin to VDD. ZL30111 Description nominal Zarlink Semiconductor Inc. Data Sheet ...
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... Functional Description The ZL30111 POTS line card PLL contains a digital phase-locked loop (DPLL), which provides timing and synchronization for SLIC/CODEC devices. Figure functional block diagram which is described in the following sections. 2.1 Reference Monitor The input reference is monitored by two reference monitor blocks. The block diagram of reference monitoring is shown in Figure 3. The reference frequency is detected and the clock is continuously monitored for two independent criteria that indicate abnormal behavior of the reference signal, for example ...
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... Digital Phase Lock Loop (DPLL) The DPLL of the ZL30111 consists of a phase detector, a loop filter and a digitally controlled oscillator. Phase Detector - the phase detector compares the input reference signal to the feedback signal and provides an error signal corresponding to the phase difference between the two. ...
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... When the ZL30111 comes out of RESET it will initially go into Freerun mode and generate a clock with the accuracy of its freerunning local oscillator (see Figure 4). If the ZL30111 determines that its selected reference is disrupted (see Figure 3), it will remain in Freerun until the selected reference is no longer disrupted ...
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... The presence of input jitter makes it difficult to define when the PLL is locked as it may not be able to align its output to the input within the required phase distance, dependent on the PLL bandwidth and the input jitter amplitude and frequency. ZL30111 11 Zarlink Semiconductor Inc. Data Sheet ...
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... When selecting a clock oscillator, numerous parameters must be considered. This includes absolute frequency, frequency change over temperature, output rise and fall times, output levels, duty cycle and phase noise. The output clock should be connected directly (not AC coupled) to the OSCi input of the ZL30111, and the OSCo output should be left open as shown in Figure 5. ...
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... A typical crystal oscillator specification is shown in Table 2. 1 Frequency 2 Tolerance 3 Oscillation mode 4 Resonance mode 5 Load capacitance 6 Maximum series resistance ZL30111 20 MHz as required (better than +/-50ppm) fundamental parallel as required 50 Ω Table 2 - Crystal Oscillator Specification 13 Zarlink Semiconductor Inc. Data Sheet . ...
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... Power Up Sequence The ZL30111 requires that the 3.3 V supply is not powered up after the 1.8 V supply. This is to prevent the risk of latch-up due to the presence of protection diodes in the IO pads. Two options are given: 1. Power-up the 3.3 V supply fully first, then power up the 1.8 V supply 2. Power up the 3.3 V supply and the 1.8 V supply simultaneously, ensuring that the 3.3 V supply is never lower than a few hundred millivolts below the 1 ...
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... Exceeding these values may cause permanent damage. Functional operation under these conditions is not implied. * Voltages are with respect to ground (GND) unless otherwise stated. Recommended Operating Conditions* Characteristics 1 Supply voltage 2 Core supply voltage 3 Operating temperature 4 Input Voltage * Voltages are with respect to ground (GND) unless otherwise stated. ZL30111 Symbol Min. V -0.5 DD_R V -0.5 CORE_R V -0.5 PIN V -0 ...
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... Rise and fall threshold voltage low * Supply voltage and operating temperature are as per Recommended Operating Conditions. * Voltages are with respect to ground (GND) unless otherwise stated. ALL SIGNALS t t IF, OF Figure 7 - Timing Parameter Measurement Voltage Levels ZL30111 Sym. Min. Max. Units I 3.0 6.5 DDS ...
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... MHz reference input to C8o delay 5 8.192 MHz reference input to F8o delay 6 19.44 MHz reference input to F8o delay * Supply voltage and operating temperature are as per Recommended Operating Conditions. t REF<xx>P REF output clock with the same frequency as REF F8o ZL30111 Symbol t REF8KP t REF2P t REF8P t REF16P t REFW Symbol ...
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... C8o delay 10 Output clock and frame pulse rise time 11 Output clock and frame pulse fall time * Supply voltage and operating temperature are as per Recommended Operating Conditions and 30 pF load. F8o C2o F4o C4o C8o ZL30111 Sym. Min. t 243 C2L t -1.0 C2D t 243 F4L t ...
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... Supply voltage and operating temperature are as per Recommended Operating Conditions. Performance Characteristics* - Unfiltered Intrinsic Jitter Characteristics 1 C2o (2.048 MHz) 2 C4o (4.096 MHz) 3 C8o (8.192 MHz) 4 F4o (8 kHz) 5 F8o (8 kHz) * Supply voltage and operating temperature are as per Recommended Operating Conditions. ZL30111 Min. Typ. Max. Units -130 +130 ppm 1 1 Max. [ ...
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... Zarlink Semiconductor 2002 All rights reserved. ISSUE ACN DATE APPRD. Package Code Previous package codes ...
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... For more information about all Zarlink products Information relating to products and services furnished herein by Zarlink Semiconductor Inc. or its subsidiaries (collectively “Zarlink”) is believed to be reliable. However, Zarlink assumes no liability for errors that may appear in this publication, or for liability otherwise arising from the application or use of any such information, product or service or for any infringement of patents or other intellectual property rights owned by third parties which may result from such application or use ...