zl30110 Zarlink Semiconductor, zl30110 Datasheet - Page 8

• Manufacturer Part Number: zl30110
• Description: Telecom Rate Conversion Dpll
• Manufacturer: Zarlink Semiconductor

3.0
3.1
The input reference is monitored by two reference monitor blocks. The block diagram of reference monitoring is
shown in Figure 3. The reference frequency is detected and the clock is continuously monitored for two
independent criteria that indicate abnormal behavior of the reference signal, for example; loss of clock or excessive
level of frequency error. To ensure proper operation of the reference monitor circuit, the minimum input pulse
width restriction of 15 nsec must be observed.
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Exceeding the thresholds of any of the monitors forces the corresponding REF_FAIL pin to go high. The single
cycle and coarse frequency failure flags force the DPLL into FreeRun mode.
REF
Reference Frequency Detector (RFD): This detector determines whether the frequency of the reference
clock is 8 kHz, 2.048 MHz, 8.192 MHz or 16.384 MHz and provides this information to the various monitor
circuits and the phase detector circuit of the DPLL.
Coarse Frequency Monitor (CFM): This circuit monitors the reference frequency over intervals of
approximately 30 µs to quickly detect large frequency changes.
Single Cycle Monitor (SCM): This detector checks the period of a single clock cycle to detect large phase
hits or the complete loss of the clock.
Reference Monitor
Functional Description
Reference Frequency
Coarse Frequency
Single Cycle
Detector
Monitor
Monitor
Figure 3 - Reference Monitor Circuit
Zarlink Semiconductor Inc.
ZL30110
OR
8
Mode select
state machine
DPLL in FreeRun Mode
REF_FAIL
Data Sheet