zl30130 Zarlink Semiconductor, zl30130 Datasheet - Page 4

• Manufacturer Part Number: zl30130
• Description: Oc-12/stm-4 Sonet/sdh/gbe Stratum 2/3/3e System Synchronizer/sets
• Manufacturer: Zarlink Semiconductor

Status
Serial Interface
Pin #
C2
D2
D1
D3
H1
G1
G2
K1
E2
F1
E3
J1
J2
dpll1_mod_sel0
dpll1_mod_sel1
dpll1_holdover
cs_b_asel0
dpll1_lock
slave_en
diff0_en
diff1_en
sck_scl
si_sda
i2c_en
Name
int_b
so
Type
I/O
I/B
I/B
I
I
I
I
O
O
O
I
O
I
u
u
u
u
u
u
DPLL1 Mode Select 1:0 (LVCMOS, Schmitt Trigger). During reset, the levels
on these pins determine the default mode of operation for DPLL1 (Automatic,
Normal, Holdover or Freerun). After reset, the mode of operation can be
controlled directly with these pins, or by accessing the dpll1_modesel register
(0x1F) through the serial interface. This pin is internally pulled up to Vdd.
Master/Slave control (LVCMOS, Schmitt Trigger). This pin selects the mode of
operation for the device. If set high, slave mode is selected. If set low, master
mode is selected. This feature can also be controlled through software registers.
This pin is internally pulled up to Vdd.
Differential Output 0 Enable (LVCMOS, Schmitt Trigger). When set high, the
differential LVPECL output 0 driver is enabled. When set low, the differential
driver is tristated reducing power consumption. This pin is internally pulled up to
Vdd.
Differential Output 1 Enable (LVCMOS, Schmitt Trigger). When set high, the
differential LVPECL output 1 driver is enabled. When set low, the differential
driver is tristated reducing power consumption.This pin is internally pulled up to
Vdd.
Lock Indicator (LVCMOS). This is the lock indicator pin for DPLL1. This output
goes high when DPLL1’s output is frequency and phase locked to the input
reference.
Holdover Indicator (LVCMOS). This pin goes high when DPLL1 enters the
holdover mode.
Clock for Serial Interface (LVCMOS). Serial interface clock. When i2c_en = 0,
this pin acts as the sck pin for the serial interface. When i2c_en = 1, this pin acts
as the scl pin (bidirectional) for the I
Serial Interface Input (LVCMOS). Serial interface data pin. When i2c_en = 0,
this pin acts as the si pin for the serial interface. When i2c_en = 1, this pin acts as
the sda pin (bidirectional) for the I
Serial Interface Output (LVCMOS). Serial interface data output. When i2c_en =
0, this pin acts as the so pin for the serial interface. When i2c_en = 1, this pin is
unused and should be left unconnected.
Chip Select/Address Select 0 for the Serial Interface (LVCMOS). Serial
interface chip select. When i2c_en = 0, this pin acts as the cs pin (active low) for
the serial interface. When i2c_en = 1, this pin acts as the asel0 pin for the I
interface.
Interrupt Pin (LVCMOS). Indicates a change of device status prompting the
processor to read the enabled interrupt service registers (ISR). This pin is an
open drain, active low and requires an external pulled up to VDD.
I
low, the SPI interface is enabled. Internally pull-up to Vdd.
2
C Interface Enable (LVCMOS). If set high, the I
Zarlink Semiconductor Inc.
ZL30130
7
2
Description
C interface.
2
C interface.
2
C interface is enabled, if set
Short Form Data Sheet
2
C