zl30146 Zarlink Semiconductor, zl30146 Datasheet
zl30146
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zl30146 Summary of contents
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... SONET/SDH line cards up to OC-192/STM-64 Rx DPLL ref m ref /sync DPLL I2C/SPI JTAG Figure 1 - Functional Block Diagram 1 Zarlink Semiconductor Inc. ZL30146 Short Form Data Sheet February 2009 64 Pin CABGA Trays 64 Pin CABGA* Trays p_clk Program m able ...
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... Each path is controlled with separate DPLLs (Tx DPLL, Rx DPLL) which are both independently configurable through the serial interface (SPI Figure 2. In this application, the ZL30146 translates the 19.44 MHz clock from the telecom rate backplane (system timing bus), translates the frequency to 622.08 MHz or 156.25 MHz for the PHY Tx clock, and filters the jitter to ensure compliance with the related standards ...
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... For more information about all Zarlink products Information relating to products and services furnished herein by Zarlink Semiconductor Inc. or its subsidiaries (collectively “Zarlink”) is believed to be reliable. However, Zarlink assumes no liability for errors that may appear in this publication, or for liability otherwise arising from the application or use of any such information, product or service or for any infringement of patents or other intellectual property rights owned by third parties which may result from such application or use ...