mt90810ap Zarlink Semiconductor, mt90810ap Datasheet - Page 10

• Manufacturer Part Number: mt90810ap
• Description: 256 X 128 Channels Flexible Mvip Interface Circuit Fmic
• Manufacturer: Zarlink Semiconductor

MT90810
Data Sheet
Please note that the digital PLL and analog PLL combination may not meet some international standards for jitter
performance. In cases where strict idle jitter specifications must be met, an external custom PLL may be required
and the internal analog PLL should be disabled (refer to PLL Diagnostic section for further details).
6. Local Output Clock Control
The FMIC provides four output clocks which are always driven off of the device. The FRAME output clock has a
duty cycle and period equal to the MVIP F0 signal. The CLK2 and CLK4 output clocks are identical to the MVIP C2
and C4 clocks, respectively. The CLK8 output provides a 8.192 MHz clock. The frame pulse and output clocks may
be used to provide framing and clocking signals to serial interfaces other than ST-BUS, such as, GCI bus. Timing
diagrams and parameters are provided in Figures 19 and 20 along with the associated table.
The local output clock control register is defined in Table 11 - “Local Clock Control (LOC_CLK) Register”. The
register allows the user to program the polarity of the four local output clocks. In addition, the register contains four
read-only bits which indicate the logic levels on EX_8KA, EX_8KB, DACK0 and DACK1 input pins of the device.
7. Local Serial Interface
The local serial interface is implemented on 4 input pins LDI[0:3] and four output pins LDO[0:3]. It can be
programmed in one of four different configurations by setting the appropriate bits in the SER_MODE register (refer
to Figure 7 - “Serial Mode (SER_MODE) Register”).
In serial configuration one, the data rate is set to 2 Mb/s. Each input stream is associated with a serial input pin and
each serial output stream is associated with a serial output pin. There are 32 channels per pin.
In serial configuration two, the data rate is set to 4 Mb/s. Local streams 0 and 1 are multiplexed onto input and
output pins LDI[0] and LDO[0] and streams 2 and 3 are multiplexed onto input and output pins LDI[2] and LDO[2].
There are 64 channels per pin and the streams are multiplexed onto the pins as shown in Table 12 - “SER_CNFG
bits (control configuration of local serial streams)”.
In serial configuration three, the data rate is set to 8 Mb/s. All four local streams are multiplexed onto pins LDI[0]
and LDO[0]. There are 128 channels per pin and the streams are multiplexed onto the pins as shown in Table 12 -
“SER_CNFG bits (control configuration of local serial streams)”.
In serial configuration four, the data rate is set to 2 Mb/s for streams 0 and 1 and 4 Mb/s for streams 2 and 3.
Streams 0 and 1 are associated with serial pins LDI/O[0] and LDI/O[1], respectively. Streams 2 and 3 are
multiplexed onto pin LDI[2] and LDO[2]. The streams are multiplexed onto the pins as shown in Table 12 -
“SER_CNFG bits (control configuration of local serial streams)”.
8. Programmable Framing Signals
The FMIC provides two groups of independently programmable output framing signals:
FGA[0:11] group A output framing signals are programmed by frame start register A (FRMA_STRT) and frame
mode register A (FRMA_MODE). FGB[0:11] group B output framing signals are programmed by frame start register
B (FRMB_STRT) and frame mode register B (FRMB_MODE).
The framing signals may be used to drive serial buses interfaces other than ST-BUS.
The functional characteristics of a group of framing output signals is controlled by MODE bits in the frame mode
register. Table 13 - “Frame Group Mode bits” defines the various modes.
In mode 0, the frame group output depends on the status of bits in the frame start and frame mode registers. The
values of the bits in frame start register x (x is either A for group A or B for group B) are driven out on pins FGx[0:7]
and the values of bits 0 to 3 in frame mode register x are driven out on pins FGx[8:11]. This mode is selected after
device reset when all bits in both registers are cleared.
In mode 1, the first four outputs of the frame group FGx[0:3] are available for programmed output as in mode 0. The
other 8 outputs of each frame group are available as output drive enables for the MVIP DSI/DSO channels within
the streams. FGA4 to FGA11 outputs correspond to output drive enables for the MVIP DSo channels within streams
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