mt90810ap Zarlink Semiconductor, mt90810ap Datasheet - Page 3

• Manufacturer Part Number: mt90810ap
• Description: 256 X 128 Channels Flexible Mvip Interface Circuit Fmic
• Manufacturer: Zarlink Semiconductor

Pin Description
58, 60,
63, 67,
70, 72,
59, 61,
64, 68,
71, 73,
80, 82,
87, 88,
100, 1,
2, 3, 5,
20, 33,
46, 57,
69, 81,
6, 7, 8,
28, 39,
51, 62,
76, 84,
74, 77
75, 78
83, 85
89, 90
9, 14,
Pin #
55
56
54
53
91
92
94
95
97
98
96
99
4
FGA[0:11]
FGB[0:11]
LDO[0:3]
DSo[0:7]
EX_8KA
EX_8KB
DSi[0:7]
LDI[0:3]
FRAME
SEC8K
Name
CSTo
CLK8
CLK4
CLK2
C4b
C2o
F0b
MVIP DSo Streams (Bidirectional CMOS). 2.048 Mb/s serial data streams conforming
to ST-BUS serial data stream specifications.
MVIP DSi Streams (Bidirectional CMOS). 2.048 Mb/s serial data streams conforming to
ST-BUS serial data stream specifications.
Local Output Serial Streams (Output). Serial data streams programmable to 2.048,
4.096 or 8.192 Mb/s data rates.
Local Input Serial Streams (TTL Input). Serial data streams programmable to 2.048,
4.096 or 8.192 Mb/s data rates.
Control ST-BUS Output (Output). This is a 1.024 Mb/s output. The state of each bit in
this stream is determined by the CSTo bit in connection memory high.
MVIP F0 signal (CMOS Input/Output). ST-BUS 8 kHz framing signal
MVIP C4 signal (CMOS Input/Output). ST-BUS 4.096 MHz clock
MVIP C2 signal (Output). ST-BUS 2.048 MHz clock. This pin is automatically set to
high impedance when it is not driven.
MVIP SEC8K signal (CMOS Input/Output). A secondary 8 kHz signal used either as
an input source to the on-chip digital PLL or as an output to the MVIP bus.
External 8 kHz input A (TTL Input).
External 8 kHz input B (TTL Input).
Local Frame Output Signal (Output). This 8 kHz framing signal has a duty cycle and
period equal to the MVIP F0 signal.
8 MHz Local Output Clock (Output). This is a 8 MHz clock.
4 MHz Local Output Clock (Output). This 4 MHz clock has a duty cycle and period equal
to the MVIP C4 signal.
2 MHz Local Output Clock (Output). This 2 MHz clock has a duty cycle and period equal
to the MVIP C2 signal.
Frame Group A framing signals (Output). Programmable framing signals. The frame
group outputs are determined by mode bits in the frame register to be either
programmed outputs, output drive enables for DSo, or output framing pulses for use
with local serial data streams.
Frame Group B framing signals (Output). Programmable framing signals. The frame
group outputs are determined by mode bits in the frame register to be either
programmed outputs, output drive enables for DSi, or output framing pulses for use with
local serial data streams.
Zarlink Semiconductor Inc.
MT90810
3
Description
Data Sheet