mt9079apr1 Zarlink Semiconductor, mt9079apr1 Datasheet - Page 19

• Manufacturer Part Number: mt9079apr1
• Description: Advanced Controller For E1
• Manufacturer: Zarlink Semiconductor

e) Local and remote time slot loopback. Local time slot loopback control bit LTSL = 0 normal; LTSL = 1 activate,
will loop around transmit ST-BUS time slots to the DSTo stream. Remote time slot loopback bits RTSL = 0
normal; RTSL = 1 activate, will loop around receive PCM 30 time slots towards the remote PCM 30 end.
The digital, remote, ST-BUS and payload loopbacks are located on page 1, address 15H, control bits 3 to 0. The
remote and local time slot loopbacks are controlled through control bits 4 and 5 of the per time slot control words,
pages 7 and 8.
PCM 30 Interfacing and Encoding
Bits 7 and 6 of page 1, address 15H (COD1-0) determine the PCM 30 format of the PCM 30 transmit and receive
signals. The RZ format (COD1-0 = 00) can be used where the line interface is implemented with discrete
components. In this case, the pulse width and state of TxA and TxB directly determine the width and state of the
PCM 30 pulses.
NRZ format (COD1-0 = 01) is not bipolar, and therefore, only requires a single output line and a single input line
(i.e., TxA and RxA). This signal along with a synchronous 4, 8 or 16 MHz clock can interface to a manchester or
similar encoder to produce a self-clocking code for a fibre optic transducer.
The NRZB format (default COD1-0 = 10) is used for interfacing to monolithic Line Interface Units (LIUs). With this
format pulses are present for the full bit cell, which allows the set-up and hold times to be meet easily.
The HDB3 control bit (page 1, address 15H, bit 5) selects either HDB3 encoding or alternate mark inversion (AMI)
encoding.
Performance Monitoring
MT9079 Error Counters
The MT9079 has six error counters, which can be used for maintenance testing, an ongoing measure of the quality
of a PCM 30 link and to assist the designer in meeting specifications such as CCITT I.431 and G.821. In parallel
microprocessor and serial microcontroller modes, all counters can be preset or cleared by writing to the appropriate
locations. When ST-BUS access is used, this is done by writing the value to be loaded into the counter in the
appropriate counter load word (page 2, address 18H to 1FH). The counter is loaded with the new value when the
appropriate counter load bit is toggled (page 2, address 15H).
Associated with each counter is a maskable event occurrence interrupt and a maskable counter overflow interrupt.
Overflow interrupts are useful when cumulative error counts are being recorded. For example, every time the frame
error counter overflow interrupt (FERO) occurs, 256 frame errors have been received since the last FERO interrupt.
System
System
DSTo
DSTo
DSTi
DSTi
Zarlink Semiconductor Inc.
MT9079
MT9079
MT9079
19
Tx
Rx
Tx
Rx
PCM30
PCM30
Data Sheet