mt9079apr1 Zarlink Semiconductor, mt9079apr1 Datasheet - Page 51

no-image

mt9079apr1

Manufacturer Part Number
mt9079apr1
Description
Advanced Controller For E1
Manufacturer
Zarlink Semiconductor
Datasheet
The data link transmit and receive signals are connected directly to port one. The DCLK signal is connected to INT1
so the 80C52 will be interrupted when new data link data needs to be transported.
Figure 9 illustrates a circuit that will interface the MT9079 to the MC68302 microprocessor operating at 20 MHz.
CS0 was chosen so that no external address decoding would be required. The MT9079 does not have a DTACK
output therefore, the MC68302 DTACK should be tied high. The data link interface is handled by Non-multiplexed
Serial Interface port Two (NMSI2).
Figure 10 shows how to connect a 16 MHz 80C188 microprocessor to the MT9079. The 80C188 WR and RD
signals are re-timed using the CLKOUT signal to generate a DS signal for the MT9079. The inverted form of DT/R
is used to make a R/W signal, and the ALE is used to latch the lower order address lines for the duration of the
access cycle.
MT9079 TAIS and Reset Circuit
Figure 11 illustrates a reset and transmit AIS circuit that can be implemented with the MC68302 microprocessor.
This circuit has three purposes: 1) to provide a power-on reset for the all the MT9079 devices; 2) to have all the
MT9079 devices transmit AIS during system initialization; and 3) to have all the MT9079 devices transmit AIS when
the MC68302 watch-dog time expires.
80C52
AD0-AD7
A
Figure 8 - MT9079 to 80C52 Microcontroller Interface Circuit
XTAL2
A
13
8
INT0
INT1
P1.0
P1.1
-A
ALE
-A
WR
RD
15
12
+5V
10k
D
CLR
PR
74HCT08
74HCT04
Q
74HCT74
Zarlink Semiconductor Inc.
8
3
5
74HCT04
MT9079
74HCT04
D
PR
74HCT04
51
Q
74HCT74
D
+5V
PR
Q
10k
R/W
CS
DS
S/P
A
D
DLCLK
RxDL
TxDL
IRQ
0
0
-A
-D
MT9079
4
7
Data Sheet

Related parts for mt9079apr1