mt9094apr1 Zarlink Semiconductor, mt9094apr1 Datasheet - Page 12

• Manufacturer Part Number: mt9094apr1
• Description: Fully Featured Digital Telephone Circuit With Embedded Dsp For Tone Generation And Hands Free Operation
• Manufacturer: Zarlink Semiconductor

MSAN-126. The DPhone-II ST-BUS consists of output and input serial data streams, DSTo and DSTi respectively,
a synchronous clock signal C4i, and a framing pulse F0i.
The data streams operate at 2048 kb/s and are Time Division Multiplexed into 32 identical channels of 64 kb/s
bandwidth. Frame Pulse (a 244 nSec low going pulse) is used to parse the continuous serial data streams into the
32 channel TDM frames. Each frame has a 125 µSecond period translating into an 8 kHz frame rate. Valid frame
pulse occurs when F0i is logic low coincident with a falling edge of C4i. C4i has a frequency (4096 MHz) which is
twice the data rate. This clock is used to sample the data at the _ bit-cell position on DSTi and to make data
available on DSTo at the start of the bit-cell. C4i is also used to clock the DPhone-II internal functions (i.e., DSP,
Filter/CODEC, HDLC) and to provide the channel timing requirements.
The DPhone-II uses channels 1, 2 & 3 of the 32 channel frame. These channels are always defined, beginning with
the first channel after frame pulse, as shown in Figure 6 (DSTi and DSTo channel assignments). Channels are
enabled independently by the three control bits Ch
(address15h).
Ch
Ch
Transmit PCM on DSTo
When high, PCM from the Filter/CODEC and DSP is transmitted on DSTo in the selected ST-BUS channel. When low,
DSTo is forced to logic 0 for the corresponding timeslot. If both Ch
Receive PCM from DSTi
When high, PCM from DSTi is routed to the DSP and Filter/CODEC in the associated channel. If both Ch
Ch
New Call Tone
The New Call Tone Generator produces a frequency shifted square-wave used to toggle the speaker driver outputs.
This is intended for use where a ringing signal is required concurrently with an already established voice
conversation in the handset.
Programming of the DSP for New Call generator is exactly as is done for the tone ringer micro-program except that
the OPT bit (DSP Control Register, address 1Eh) is set high. In this mode the DSP does not produce a frequency
shifted squarewave output to the filter CODEC section. Instead the DSP uses the contents of the tone coefficient
registers, along with the tone warble rate register, to produce a gated squarewave control signal output which
toggles between the programmed frequencies. This control signal is routed to the New Call Tone block when the
NCT EN control bit is set (General Control Register, address 0Fh). NCT EN also enables a separate gain control
block, for controlling the loudness of the generated ringing signal. With the gain control block set to 0 dB the output
is at maximum or 6 volts p-p. Attenuation of the applied signal, in three steps of 8 dB, provide the four settings for
New Call tone (0, -8, -16, -24 dB). The NCT gain bits (NCTG
2 (address 0Bh).
1
2
3
EN - C-Channel
EN and Ch
EN are enabled the default is to channel 2.
Channel 1 conveys the control/status information for Zarlink’s layer 1 transceiver. The full 64 kb/s bandwidth is
Channels 2 and 3 are the B1 and B2 channels, respectively. These bits (Ch
available and is assigned according to which transceiver is being used. Consult the data sheet for the selected
transceiver for its bit definitions and order of bit transfer. When this bit is high register data is transmitted on DSTo.
When low, this timeslot is tri-stated on DSTo. Receive C-Channel data (DSTi) is always routed to the register
regardless of this control bit's logic state. C-channel data is transferred on the ST-BUS MSB first by the DPhone-II.
PCM channels from/to the DPhone-II as required.
3
EN - B1-Channel and B2-Channel
Zarlink Semiconductor Inc.
MT9094
12
1
En -Ch
0
-NCTG
2
EN and Ch
3
En residing in the Timing Control Register
1
) reside in the FCODEC Gain Control Register
3
EN are enabled, default is to channel 2.
2
EN and Ch
3
EN) are used to enable the
Data Sheet
2
EN and