zl50015qcg1 Zarlink Semiconductor, zl50015qcg1 Datasheet - Page 13

• Manufacturer Part Number: zl50015qcg1
• Description: Enhanced 1 K Channel Tdm Switch With Rate Conversion
• Manufacturer: Zarlink Semiconductor

B7, C7, B5,
PBGA Pin
G15, G14,
H14, D11,
E15, F14
Number
B10
F15
B11
J6
LQFP Pin
102, 106,
100, 104,
170, 172,
174, 227
Number
110, 112
108
155
154
FPo_OFF0 - 2
Pin Name
CKo0 - 3
FPo0 - 3
CKi
FPi
Zarlink Semiconductor Inc.
ST-BUS/GCI-Bus Frame Pulse Outputs 0 to 3 (5 V-Tolerant
Three-state Outputs)
FPo0: 8 kHz frame pulse corresponding to the 4.096 MHz output
clock of CKo0.
FPo1: 8 kHz frame pulse corresponding to the 8.192 MHz output
clock of CKo1.
FPo2: 8 kHz frame pulse corresponding to 16.384 MHz output
clock of CKo2.
FPo3: Programmable 8 kHz frame pulse corresponding to
4.096 MHz, 8.192 MHz, 16.384 MHz, or 32.768 MHz output clock
of CKo3.
Generated Offset Frame Pulse Outputs 0 to 2 (5 V-Tolerant
Three-state Outputs)
Individually programmable 8 kHz frame pulses, offset from the
output frame boundary by a programmable number of channels.
ST-BUS/GCI-Bus Clock Outputs 0 to 3 (5 V-Tolerant
Three-state Outputs)
CKo0: 4.096 MHz output clock.
CKo1: 8.192 MHz output clock.
CKo2: 16.384 MHz output clock.
CKo3: 4.096 MHz, 8.192 MHz or 16.384 MHz programmable
output clock. 32.768MHz if in multiplied clock mode.
ST-BUS/GCI-Bus
Schmitt-Triggered Input)
This pin accepts the frame pulse which stays active for 61 ns,
122 ns or 244 ns at the frame boundary. The frame pulse
frequency is 8 kHz. The frame pulse associated with the CKi must
be applied to this pin. If the data rate is 16.384 Mbps, a 61 ns wide
frame pulse must be used. By default, the device accepts a
negative frame pulse in ST-BUS format, but it can accept a
positive frame pulse instead if the FPINP bit is set high in the
Control Register (CR). It can accept a GCI-formatted frame pulse
by programming the FPINPOS bit in the Control Register (CR) to
high.
ST-BUS/GCI-Bus Clock Input (5 V-Tolerant Schmitt-Triggered
Input)
This pin accepts a 4.096 MHz, 8.192 MHz or 16.384 MHz clock.
In divided clock mode the clock frequency applied to this pin must
be twice the highest input or output data rate. In multiplied
clock mode the clock frequency applied to this pin must be twice
the highest input data rate.
The exception is, when data is running at 16.384 Mbps, a 16.384
MHz clock must be used. By default, the clock falling edge defines
the input frame boundary, but the device allows the clock rising
edge to define the frame boundary by programming the CKINP bit
in the Control Register (CR).
ZL50016
13
Frame
Description
Pulse
Input
(5 V-Tolerant
Data Sheet