ZL50015 ZARLINK [Zarlink Semiconductor Inc], ZL50015 Datasheet
ZL50015
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ZL50015 Summary of contents
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... REF_FAIL1 REF_FAIL2 REF_FAIL3 OSC_EN OSC Figure 1 - ZL50015 Functional Block Diagram Zarlink Semiconductor US Patent No. 5,602,884, UK Patent No. 0772912, France Brevete S.G.D.G. 0772912; Germany DBP No. 69502724.7-08 Zarlink, ZL and the Zarlink Semiconductor logo are trademarks of Zarlink Semiconductor Inc. Copyright 2004-2005, Zarlink Semiconductor Inc. All Rights Reserved. ...
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... PBX and IP-PBX • Small and medium digital switching platforms • Remote access servers and concentrators • Wireless base stations and controllers • Multi service access platforms • Digital Loop Carriers • Computer Telephony Integration ZL50015 2 Zarlink Semiconductor Inc. Data Sheet ...
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... Mbps, 4.096 Mbps, 8.192 Mbps or 16.384 Mbps. The ZL50015 provides up to eight high impedance control outputs (STOHZ0 - 7) to support the use of external tristate drivers for the first eight output streams (STio0 - 15). The output streams can be configured to operate in bi-directional mode, in which case STi0 - 15 will be ignored ...
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... Input Frequencies Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 13.3 Output Frequencies . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 13.4 Pull-In/Hold-In Range (also called Locking Range 14.0 Jitter Performance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 14.1 Input Clock Cycle to Cycle Timing Variation Tolerance 14.2 Input Jitter Acceptance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 14.3 Jitter Transfer Function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 15.0 DPLL Specific Functions and Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 15.1 Lock Detector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 ZL50015 Table of Contents 4 Zarlink Semiconductor Inc. Data Sheet ...
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... Detailed Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 24.0 Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86 24.1 Memory Address Mappings 24.2 Connection Memory Low (CM_L) Bit Assignment 24.3 Connection Memory High (CM_H) Bit Assignment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88 25.0 Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90 25.1 OSCi Master Clock Requirement . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90 25.1.1 External Crystal Oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90 25.1.2 External Clock Oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91 26.0 DC Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92 27.0 AC Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93 ZL50015 Table of Contents 5 Zarlink Semiconductor Inc. Data Sheet ...
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... Figure 1 - ZL50015 Functional Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Figure 2 - ZL50015 256-Ball PBGA (as viewed through top of package Figure 3 - ZL50015 256-Lead LQFP (top view Figure 4 - Input Timing when CKIN1 - 0 bits = “10” in the Figure 5 - Input Timing when CKIN1 - 0 bits = “01” in the Figure 6 - Input Timing when CKIN1 - 0 = “ ...
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... Figure 49 - Output Timing (ST-BUS Format 116 ZL50015 List of Figures 7 Zarlink Semiconductor Inc. Data Sheet ...
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... Table 3 - Output Timing Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 Table 4 - Delay for Variable Delay Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 Table 5 - Connection Memory Low After Block Programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 Table 6 - Connection Memory High After Block Programming Table 7 - ZL50015 Operating Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 Table 8 - Preferred Reference Selection Options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 Table 9 - DPLL Input Reference Frequencies . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 Table 10 - Generated Output Frequencies Table 11 - Values for Single Period Limits ...
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... Table 50 - Address Map for Memory Locations (A13 = Table 51 - Connection Memory Low (CM_L) Bit Assignment when CMM = Table 52 - Connection Memory Low (CM_L) Bit Assignment when CMM = Table 53 - Connection Memory High (CM_H) Bit Assignment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89 ZL50015 List of Tables 9 Zarlink Semiconductor Inc. ...
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... Table 31, Lock Detector Threshold Register (LDTR) Bits 70 Table 34, Reference Change Control Register (RCCR) Bits ZL50015 • The on-chip DPLL’s normal, holdover, automatic, and freerun modes are now collectively referred to as DPLL timing modes instead of operation modes. This change is to avoid confusion with the two main device operating modes ...
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... STOHZ0 STio2 STOHZ2 Note: A1 corner identified by metallized marking. Note: Pinout is shown as viewed through top of package. Figure 2 - ZL50015 256-Ball PBGA (as viewed through top of package) ZL50015 DD_ STi0 CKo0 REF2 ...
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... NC NC 248 VDD_IO NC 250 VSS NC 252 NC NC 254 NC NC 256 Figure 3 - ZL50015 256-Lead LQFP (top view) ZL50015 176 174 172 170 168 166 164 162 160 158 156 154 152 150 ...
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... M5, M12, 209, 214, P3, P14, T1, 216, 218, T16 222, 223, 228, 230, 232, 235, 242, 251 ZL50015 Power Supply for the core logic: +1.8 V Power Supply for analog circuitry: +1.8 V Power Supply for I/O: +3.3 V DD_IO Power Supply for the CKo5 and CKo3 outputs: +3.3 V DD_IOA V Ground ...
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... K12 210 C13, G3 144, 208 IC_GND ZL50015 Description Test Mode Select (5 V-Tolerant Input with Internal Pull-up) JTAG signal that controls the state transitions of the TAP controller. This pin is pulled high by an internal pull-up resistor when it is not driven. Test Clock (5 V-Tolerant Schmitt-Triggered Input with Internal Pull-up) Provides the clock to the JTAG test logic ...
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... These two pins should be tied together and are typically used to select CKi = 4.096 MHz operation. See Table 7, “ZL50015 Operating Modes” on page 37 for a detailed explanation. See Table 17, “Control Register (CR) Bits” on page 53 for CKi and FPi selection using the CKIN1 - 0 bits. ...
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... G15, G14, 102, 106, FPo0 - 3 E15, F14 110, 112 ZL50015 Description Oscillator Clock Output (3.3 V Output) If OSC_EN = ‘1’, this pin should be connected MHz crystal (see Figure 23 on page 90) or left unconnected if a clock oscillator is connected to OSCi pin under normal operation (see Figure 24 on page 91) ...
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... B10 155 FPi ZL50015 Generated Offset Frame Pulse Outputs V-Tolerant Three-state Outputs) Individually programmable 8 kHz frame pulses, offset from the output frame boundary by a programmable number of channels. Generated Offset Frame Pulse Output 2 or 19.44 MHz Frame ...
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... L14, E14, 74, 115, D13, D15, 116, 117, C15 118 ZL50015 Description ST-BUS/GCI-Bus Clock Input (5 V-Tolerant Schmitt Triggered Input) This pin accepts a 4.096 MHz, 8.192 MHz or 16.384 MHz clock. The clock frequency associated with twice the highest input or output data rate must be applied to this pin when the device is operating in either Divided Slave mode or Master mode ...
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... R/W_WR R12 42 DS_RD ZL50015 Serial Output Streams High Impedance Control V-Tolerant Slew-Rate-Limited Three-state Outputs) These pins are used to enable (or disable) external three-state buffers. When an output channel is in the high impedance state, the STOHZ drives high for the duration of the corresponding output channel ...
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... FPi and CKi in Divided Slave mode. In Multiplied Slave mode, the output data streams will be driven by an internally generated clock, which is multiplied ZL50015 Address V-Tolerant Inputs) These pins form the 14-bit address bus to the internal memories and registers ...
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... Data Rates and Timing The ZL50015 has 16 serial data inputs and 16 serial data outputs. Each stream can be individually programmed to operate at 2.048 Mbps, 4.096 Mbps, 8.192 Mbps or 16.384 Mbps. Depending on the data rate there will be 32 channels, 64 channels, 128 channels or 256 channels, respectively, during a 125 µs frame. ...
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... Input Clock (CKi) and Input Frame Pulse (FPi) Timing The input clock for the ZL50015 can be arranged in one of three different ways. These different ways will be explained further in Section 11.1 to Section 11.3 on page 38. Depending on the mode of operation, the input clock, CKi, will be based on the highest data rate of either the input or both the input and output data rates. The user has to program the CKIN1 - 0 (bits the Control Register (CR) to indicate the width of the input frame pulse and the frequency of the input clock supplied to the device ...
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... FPINPOS = 1 FPi (122 ns) FPINP = 1 FPINPOS = 1 CKi (8.192 MHz) CKINP = 0 CKi (8.192 MHz) CKINP = 1 Channel 0 STi (4.096 Mbps) Figure 5 - Input Timing when CKIN1 - 0 bits = “01” in the CR ZL50015 Channel Channel Zarlink Semiconductor Inc. Data Sheet ...
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... Output Timing Generation The ZL50015 generates frame pulse and clock timing. There are five output frame pulse pins (FPo0 - 3, 5) and six output clock pins (CKo0 - 5). All output frame pulses are 8 kHz output signals. By default, the output frame boundary is defined by the falling edge of the CKo0, while FPo0 is low. At the output frame boundary, the CKo1, CKo2 and CKo3 output clocks will by default have a falling edge, while FPo1, FPo2 and FPo3 will be low ...
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... Output Clock and Frame Pulse Selection Register (OCFSR). By default, the device delivers the negative output clock format. The ZL50015 can also deliver GCI-Bus format output frame pulses by programming bits of the Output Clock and Frame Pulse Selection Register (OCFSR). As there is a separate bit setting for each frame pulse output, some of the outputs can be set to operate in ST-BUS mode and others in GCI-Bus mode ...
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... Figure 7 - Output Timing for CKo0 and FPo0 CKOFPO1EN = 1 FPO1P = 0 FPO1POS = 0 CKOFPO1EN = 1 FPO1P = 1 FPO1POS = 0 CKOFPO1EN = 1 FPO1P = 0 FPO1POS = 1 CKOFPO1EN = 1 FPO1P = 1 FPO1POS = 1 CKOFPO1EN = 1 CKO1P = 0 CKo1 = 8.192 MHz CKOFPO1EN = 1 CKO1P = 1 CKo1 = 8.192 MHz Figure 8 - Output Timing for CKo1 and FPo1 ZL50015 26 Zarlink Semiconductor Inc. Data Sheet ...
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... When CKOFPO3SEL1-0 = “01,” the output for FPo3 and CKo3 follow the same as Figure 8: Output Timing for CKo1 and FPo1 When CKOFPO3SEL1-0 = “10,” the output for FPo3 and CKo3 follow the same as Figure 9: Output Timing for CKo2 and FPo2 Figure 10 - Output Timing for CKo3 and FPo3 with CKoFPo3SEL1-0=”11” ZL50015 27 Zarlink Semiconductor Inc. ...
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... While there is no frame pulse output directly tied to the CKo4, the output clocks are based on the frame pulse generated by FPo0 FPo5 (FPo_OFF2) FP19EN = 1 CKO5EN = 1 CK5 = 19.44 MHz Figure 12 - Output Timing for CKo5 and FPo5 (FPo_OFF2) ZL50015 Figure 11 - Output Timing for CKo4 28 Zarlink Semiconductor Inc. Data Sheet ...
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... Bit Delay = 1 Note: Last Channel = 31, 63, 127 and 255 for 2.048, 4.096, 8.192 and 16.384 Mbps modes respectively. Figure 13 - Input Bit Delay Timing Diagram (ST-BUS) ZL50015 Channel 0 Channel ...
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... Input Bit Sampling Point Programming In addition to the input bit delay feature, the ZL50015 allows users to change the sampling point of the input bit by programming STIN[n]SMP 1-0 (bits the Stream Input Control Register (SICR0 - 15). For input streams operating at any rate except 16.384 Mbps, the default sampling point is at 3/4 bit and users can change the sampling point to 1/4, 1/2, 3/4 or 4/4 bit position ...
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... By default, all output streams have zero bit advancement such that bit 7 is the first bit that appears after the output frame boundary (assuming ST-BUS formatting). The output advancement is enabled by STO[n] (bits the Stream Output Control Register (SOCR0 - 15) as described in Table 45 on page 83. The output bit advancement can vary from bits. ZL50015 ...
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... STo[n]FA1 ( Mbps) Note: Last Channel = 31, 63, 127 and 255 for 2.048, 4.096, 8.192 and 16.384 Mbps modes respectively. Figure 17 - Output Fractional Bit Advancement Timing Diagram (ST-BUS) ZL50015 Channel ...
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... Control Register (CR) must be set before V/C (bit 14) in the Connection Memory Low when CMM = 0. If the VAREN bit is not set and the device is programmed for variable delay mode, the information read on the output stream will not be valid. ZL50015 HiZ CH2 ...
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... The constant delay mode is controlled by V/C (bit 14) in the Connection Memory Low when CMM = 0. When this bit is set low, the channel is in constant delay mode. If VAREN (bit 4) in the Control Register (CR) is set (to enable variable throughput delay on a chip-wide basis), the device can still be programmed to operate in constant delay mode. ZL50015 n-m < < n-m < frame - (m-n) ...
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... UAEN (bit 15) in the Connection Memory Low. When CMM (bit 0) of the Connection Memory Low (CM_L) is programmed high, the ZL50015 will operate in one of the special modes described in Table 52 on page 88. When the per-channel message mode is enabled, MSG7 - 0 (bit the Connection Memory Low (CM_L) will be output via the serial data stream as message output data. When the per-channel message mode is enabled, the µ ...
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... Slave modes, output clocks and frame pulses are generated based on CKi and FPi. The difference is that, in Divided Slave mode, the output clocks and frame pulses are directly divided from CKi/FPi, while in Multiplied Slave mode, the output clocks and frame pulses are generated from an internal high-speed clock synchronized to CKi ZL50015 11 10 ...
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... Note that an external oscillator is required whenever the DPLL is used. Table 7, “ZL50015 Operating Modes” on page 37 summarizes the different modes of operation available within the ZL50015. Each Major mode has various associated Minor modes that are determined by setting the relevant Input Control pins and Control Register bits (Table 17, “Control Register (CR) Bits” on page 53) indicated in the table. ...
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... In this mode, the state machine controls the DPLL based on the settings in the registers and the quality of the reference input clocks. The DPLL is internally either in normal or in holdover mode. In the following two sections, the reference selection and state machine operation in automatic mode will be explained in more details. ZL50015 38 Zarlink Semiconductor Inc. ...
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... Free run Ref 0 failed Holdover 0 Ref 0 Ref 0 valid Holdover 3 Ref 3 Figure Preferred Reference (Round Robin) with Ref 0-3 available ZL50015 Start Ref 0 and 1 failed and (Ref 2 or Ref 3 valid) All Ref failed All Ref failed All Ref failed All Ref failed ...
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... Primary Reference (Preferred) Option 1 Option 2 Option 3 Option 4 Table 8 - Preferred Reference Selection Options Figure 22 shows the state diagram for the four valid options of automatic reference switching with a preferred reference. ZL50015 Ref 0 Ref 1 Ref 2 Ref 3 40 Zarlink Semiconductor Inc. Data Sheet Secondary Reference ...
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... Ref 3 DPLL will switch between Ref 3 and Ref 0 Note : other combinations not shown here are invalid settings and should not be used Figure 22 - Automatic Reference Switching State Diagrams with Preferred Reference ZL50015 Ref 0 and 1 failed Ref 0 valid Holdover 0 Ref 0 failed Ref 0 and 1 failed ...
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... Table 27 on page 64, Table 35 on page 71 and Table 41 on page 77 for the detailed bit description of the DPLL Control Register (DPLLCR), Reference Frequency Register (RFR), Reference Change Status Register (RCSR) and Reference Frequency Status Register (RFSR), respectively. ZL50015 8 kHz 1.544 MHz (DS1) 2 ...
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... Jitter Performance 14.1 Input Clock Cycle to Cycle Timing Variation Tolerance The ZL50015 has an exceptional cycle to cycle timing variation tolerance of 20 ns. This allows the ZL50015 to synchronize off a low cost DPLL when either Divided Slave mode or Multiplied Slave mode. 14.2 Input Jitter Acceptance The input jitter acceptance is specified in standards as the minimum amount of jitter of a certain frequency on the input clock that the DPLL must accept without making cycle slips or losing lock ...
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... The Reference Status Register (RSR) reports the status of the reference monitors. The register bits are described in Table 39 on page 74. The Reference Mask Register (RMR) allows users to ignore the monitoring features of the reference monitors. See Table 40 on page 75 for details. ZL50015 44 Zarlink Semiconductor Inc. ...
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... The device has two sets of limits the Stratum 4E default limits and the Relaxed Stratum 4E limits (see Table 12 on page 45). The ST4_LIM bit in Table 26, DPLL Control Register (DPLLCR) Bits is used to select between the two sets of limits. Far Upper Limit Near Upper Limit Nominal Value Near Lower Limit Far Lower Limit ZL50015 Reference Comment Frequency 8 kHz 10 UIp-p 1.544 MHz 0.3 UIp-p 2 ...
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... Refer to Figure 26 on page 94, Figure 27 on page 95, Figure 28 on page 96 and Figure 29 on page 97 for the microprocessor timing. 17.0 Device Reset and Initialization The RESET pin is used to reset the ZL50015. When this pin is low, the following functions are performed: • synchronously puts the microprocessor port in a reset state • ...
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... Pseudo random Bit Generation and Error Detection The ZL50015 has one Bit Error Rate (BER) transmitter and one BER receiver for each pair of input and output streams, resulting in 16 transmitters connected to the output streams and 16 receivers associated with the input streams. Each transmitter can generate a BER sequence with a pattern of 2 Each transmitter can start at any location on the stream and will last for a minimum of 1 channel to a maximum of 1 frame time (125 µ ...
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... The input channel and output channel encoding law are configured independently. If the output channel coding is set to be different from the input channel, the ZL50015 performs translation between the two standards. If the input and output encoding laws are set to the same standard, no translation occurs. As the V/D (bit 4) of the Connection Memory High (CM_H) must be set on a per-channel basis not possible to translate between voice and data encoding laws ...
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... Test Access Port (TAP) Controller. 21.1 Test Access Port (TAP) The Test Access Port (TAP) accesses the ZL50015 test functions. It consists of three input pins and one output pin as follows: • Test Clock Input (TCK) - TCK provides the clock for the test logic. TCK does not interfere with any on-chip clock and thus remains independent in the functional mode ...
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... Instruction Register The ZL50015 uses the public instructions defined in the IEEE-1149.1 standard. The JTAG interface contains a four-bit instruction register. Instructions are serially loaded into the instruction register from the TDi when the TAP Controller is in its shifted-OR state. These instructions are subsequently decoded to achieve two basic functions: to select the test data register that may operate while the instruction is current and to define the serial test data register path that is used to shift data between TDi and TDo during data register scanning ...
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... H 006B R Only Reference Frequency Status Register H 006C R/W Output Jitter Control Register H 0100 - R/W Stream Input Control Registers 010F H Table 16 - Address Map for Registers (A13 = 0) ZL50015 Register Abbreviation Name CR IMS SRR OCFCR OCFSR FPOFF0 FPOFF1 FPOFF2 IFR BERFR0 BERLR0 DPLLCR RFR CFRL ...
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... R/W BER Receiver Control Registers 034F H 0360 - R Only BER Receiver Error Registers 036F H Table 16 - Address Map for Registers (A13 = 0) (continued) ZL50015 Register Abbreviation Name SIQFR0 - 15 SOCR0 - 15 BRSR0 - 15 BRLR0 - 15 BRCR0 - 15 BRER0 - 15 52 Zarlink Semiconductor Inc. Data Sheet Reset By Switch/Hardware Switch/Hardware ...
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... When SLV_DPLLEN is set in Slave mode, CKo[3:0] and FPo[3:0] are generated from CKi and FPi. CKo[5:4] and FPo[5] are locked to the selected input reference (one of REF[3:0]). In this mode of operation, the DPLL retains its functionality, including the generation of the REF_FAIL[3:0] output signals. See Table 7, “ZL50015 Operating Modes” on page 37 for more details OPM1 - 0 Operation Mode ...
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... This bit enables the STio0 - 15 and the STOHZ0 -7 serial outputs. The following table describes the HiZ control of the serial data outputs: RESET Pin Note: Unused output streams are tristated (STio = HiZ, STOHZ = Driven High). Refer to SOCR0 - 15 (bit2 - 0). Table 17 - Control Register (CR) Bits (continued) ZL50015 CKi_ FPIN CKINP FPINP CKIN LP ...
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... OPM DPLLEN 1 0 Bit Name MS1 - 0 Memory Select Bits These two bits are used to select connection memory low, connection high or data mem- ory for access by CPU: Table 17 - Control Register (CR) Bits (continued) ZL50015 CKi_ FPIN CKINP FPINP CKIN LP POS ...
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... Register is set to high and the MBPS bit in this register is set to high, the contents of the bits BPD2 - 0 are loaded into bits the Connection Memory Low. Bits the Connection Memory Low and bits Connection Memory High are zeroed. Table 18 - Internal Mode Selection Register (IMS) Bits ZL50015 ...
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... When this bit is low, the DPLL block is in normal operation. When this bit is high, the DPLL block is in software reset state. Refer to Table 16, “Address Map for Registers (A13 = 0)” on page 51 for details regarding which registers are affected. Table 19 - Software Reset Register (SRR) Bits ZL50015 ...
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... CKo0 and FPo0 Enable When this bit is high, output clock CKo0 and output frame pulse FPo0 are enabled. EN When this bit is low, CKo0 and FPo0 are in high impedance state. Table 20 - Output Clock and Frame Pulse Control Register (OCFCR) Bits ZL50015 ...
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... When this bit is low, the output clock CKo2 falling edge aligns with the frame boundary. When this bit is high, the output clock CKo2 rising edge aligns with the frame boundary. Table 21 - Output Clock and Frame Pulse Selection Register (OCFSR) Bits ZL50015 ...
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... When this bit is high, FPo0 starts from frame boundary (as defined by GCI-Bus). Note: In Divided Slave modes, CKo3 - 1 cannot exceed frequency of CKi. Note: CKo[5:4] are available in Master mode or in Slave mode with SLV_DPLLEN set. Table 21 - Output Clock and Frame Pulse Selection Register (OCFSR) Bits (continued) ZL50015 ...
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... The binary value of these bits refers to the channel offset from original frame bound- ary. Permitted channel offset values depend on bits 1-0 of this register FOF[n] FPo_OFF[n] Control bits FOF[n]C 1 Note: [n] denotes output offset frame pulse from Table 22 - FPo_OFF[n] Register (FPo_OFF[n]) Bits ZL50015 FOF[n] FOF[n] FOF[n] FOF[n] FOF[n] OFF7 ...
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... BER Error Flag[n]: If BERF[n] is high, it indicates that BER Receiver Error Register [n] (BRER[n]) is not zero. If BERF[n] is low, it indicates that BER Receiver Error Register [n] (BRER[n]) is zero. Note: [n] denotes input stream from 0 -15. Table 24 - BER Error Flag Register 0 (BERFR0) Bits - Read Only ZL50015 ...
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... When this bit is low, the DPLL module is in the operational state. When this bit is high, the DPLL module is in the power saving mode. Registers are not reset and are still accessible in the power saving mode. Table 26 - DPLL Control Register (DPLLCR) Bits ZL50015 ...
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... R2F2 - 0 Reference 2 Frequency Bits: When the RFRE bit of the DPLLCR register is high, these bits are used to select the REF2 input frequency. When the RFRE bit is low, these bits are ignored. Table 27 - Reference Frequency Register (RFR) Bits ZL50015 R3F1 ...
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... R0F2 - 0 Reference 0 Frequency Bits When the RFRE bit of the DPLLCR register is high, these bits are used to select the REF0 input frequency. When the RFRE bit is low, these bits are ignored. Table 27 - Reference Frequency Register (RFR) Bits (continued) ZL50015 ...
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... CFRL register bits represents the center frequency number (CFN) explained under CFRL register bits explanation. The default value of this register should be changed only if compensation for input oscil- lator (or crystal) frequency offset is required, and SHOULD NOT be changed in any other circumstances. Table 29 - Centre Frequency Register - Upper 10 Bits (CFRU) ZL50015 ...
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... DPLL output from its center frequency. Defined in same units as CFN in the 2's complement format. Note 1: Output frequency offset, relative to master clock, will be represented as the following: +10 ppm: CFN x 0.00001 = 440 = 01B8 -10 ppm: CFN x (-0.00001) = -440 = 7E48 Table 30 - Frequency Offset Register (FOR) Bits - Read Only ZL50015 FOF ...
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... Lock Detector Interval Bits The binary value of these bits defines the time interval that the output phase detector must be below the lock detect threshold to declare lock. Unsigned representation of the LDI bits is defined intervals. Table 32 - Lock Detector Interval Register (LDIR) Bits ZL50015 ...
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... DPLL output clock and the phase offset value is maintained. When this bit is high, MTIE circuit is in its reset state and the phase offset value is reset to zero, causing alignment of the DPLL output clocks to nearest edge of the selected input reference. Table 34 - Reference Change Control Register (RCCR) Bits ZL50015 ...
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... Section 12.1.3.2, “Automatic Reference Switching With Preferences“ on page 40 for more details FDM1 - 0 Force DPLL Timing Mode These bits force the DPLL into one of the valid operation modes. Table 34 - Reference Change Control Register (RCCR) Bits (continued) ZL50015 ...
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... These bits represent the frequency of the selected reference indicated by the reference bits (RES1 - 0) in this register RES1 - 0 Reference Select Indicator Bits: These bits indicate which one of the four reference inputs (REF0 - 3 pins) is being selected by the device. Table 35 - Reference Change Status Register (RCSR) Bits - Read Only ZL50015 ...
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... If any of these bits are set, the interrupt output will become active unless the Interrupt Mask Register (IMR) has a high value for that particular bit. Note 2: Any of these bits can be cleared by setting the appropriate bit in the Interrupt Clear Register. Table 36 - Interrupt Register (IR) Bits - Read Only ZL50015 ...
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... Writing a “1” to any bit in this register will clear the corresponding bit in the Interrupt Register (IR). The Interrupt Clear Register is self-clearing, i.e. once it has completed its action, the ICR register bit returns Unused Reserved In normal functional mode, this bit MUST be set to one. Table 38 - Interrupt Clear Register (ICR) Bits ZL50015 ...
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... Reference 1 Single Period Lower Limit Fail Bit If the device sets this bit to high, the input REF1 fails the single-period lower limit check. (See Table 11, “Values for Single Period Limits” on page 45) Table 39 - Reference Failure Status Register (RSR) Bits - Read Only ZL50015 ...
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... When this bit is high, it masks the multi-period upper limit check (or forces pass) for REF3. 13 R3ML Reference 3 Single-period Lower Limit Mask Bit When this bit is high, it masks the single-period lower limit check (or forces pass) for REF3. Table 40 - Reference Mask Register (RMR) Bits ZL50015 ...
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... When this bit is high, it masks the multi-period lower limit check (or forces pass) for REF0. 2 R0MMU Reference 0 Multi-period Upper Limit Mask Bit When this bit is high, it masks the multi-period upper limit check (or forces pass) for REF0. Table 40 - Reference Mask Register (RMR) Bits (continued) ZL50015 ...
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... R3FS 2 Bit Name Unused Reserved. In normal functional mode, these bits are zero R3FS2 - 0 Reference 3 Frequency Status Bits These bits report detected frequency of REF3. Table 41 - Reference Frequency Status Register (RFSR) Bits - Read only ZL50015 MMU ...
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... R1FS2 - 0 Reference 1 Frequency Status Bits: These bits report detected frequency of REF1. R1FS2 R0FS2 - 0 Reference 0 Frequency Status Bits: These bits report detected frequency of REF0. R0FS2 Table 41 - Reference Frequency Status Register (RFSR) Bits - Read only (continued) ZL50015 R3FS R3FS R2FS ...
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... The binary value of these bits refers to the number of bits that the input stream will be delayed relative to FPi. The maximum value is 7. Zero means no delay. Input Data Sampling Point Selection Bits STIN[n]SMP1 - 0 STIN[n]SMP1-0 Table 43 - Stream Input Control Register (SICR0 - 15) Bits ZL50015 ...
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... Bit Name STIN[n]DR3 - 0 Input Data Rate Selection Bits: Note: [n] denotes input stream from 0 - 15. Table 43 - Stream Input Control Register (SICR0 - 15) Bits (continued) ZL50015 STIN[n] STIN[n] STIN[n] STIN[n] STIN[n] BD2 BD1 BD0 SMP1 Description ...
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... These three bits are used to control STi[n]’s quadrant frame 2, which is defined as Ch16 to 23, Ch32 to 47, Ch64 to 95 and Ch128 to 191 for the 2.048 Mbps, 4.096 Mbps, 8.192 Mbps, and 16.384 Mbps modes respectively. Table 44 - Stream Input Quadrant Frame Register (SIQFR0 - 15) Bits ZL50015 ...
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... These three bits are used to control STi[n]’s quadrant frame 0, which is defined as Ch0 to 7, Ch0 to 15, Ch0 to 31 and Ch0 to 63 for the 2.048 Mbps, 4.096 Mbps, 8.192 Mbps, and 16.384 Mbps modes respectively. Note: [n] denotes input stream from 0 - 15. Table 44 - Stream Input Quadrant Frame Register (SIQFR0 - 15) Bits (continued) ZL50015 ...
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... The binary value of these bits refers to the number of bits that the output stream advanced relative to FPo. The maximum value is 7. Zero means no advancement STO[n]DR3 - 0 Output Data Rate Selection Bits Note: [n] denotes output stream from 0 - 15. Table 45 - Stream Output Control Register (SOCR0 - 15) Bits ZL50015 STOHZ STO[n] ...
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... Mbps, 4.096 Mbps, 8.192 Mbps and 16.384 Mbps respectively. The minimum number of BER channels these bits are set to zero, no BER test will be performed. Note: [n] denotes input stream from Table 47 - BER Receiver Length Register [n] (BRLR[n]) Bits ZL50015 ...
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... The binary value of these bits refers to the bit error counts. When it reaches its maxi- mum value of 0xFFFF, the value will be held and will not rollover. Note: [n] denotes input stream from Table 49 - BER Receiver Error Register [n] (BRER[n]) Bits - Read Only ZL50015 ...
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... Channels are used when serial stream is at 4.096 Mbps. 4. Channels 0 to 127 are used when serial stream is at 8.192 Mbps. 5. Channels 0 to 255 are used when serial stream is at 16.384 Mbps. Table 50 - Address Map for Memory Locations (A13 = 1) ZL50015 A8 Stream [n] A7 ...
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... If this is low, the connection memory is in the normal switching mode. Bit13 - 1 are the source stream number and channel number. µ- Note: For proper law/A-law conversion, the CM_H bits should be set before Bit 15 (UAEN bit) is set to high. Table 51 - Connection Memory Low (CM_L) Bit Assignment when CMM = 0 ZL50015 ...
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... ICL and OCL bits select between various bit inverting protocols. These coding laws are illustrated in the following table. If the ICL is different than the OCL, all data bytes passing through the switch on that particular connection are translated between the indicated laws. If the ICL and the OCL are the same, no coding law translation is performed. ZL50015 10 9 ...
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... Output Coding Law µ- Note 1: For proper law/A-law conversion, the CM_H bits should be set before Bit 15 of CM_L is set to high. Note 2: Refer to G.711 standard for detail information of different laws. Table 53 - Connection Memory High (CM_H) Bit Assignment ZL50015 ...
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... Typically, for a 20 MHz crystal specified with load capacitance, each 1 pF change in load capacitance contributes approximately 9 ppm to the frequency deviation. Consequently, capacitor tolerances and stray capacitances have a major effect on the accuracy of the oscillator frequency. The trimmer capacitor shown in Figure 23 on page 90 may be used to compensate for capacitive effects. ZL50015 OSCi 20 MHz Ω ...
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... Figure 24 on page 91 buffered version of the 20 MHz input clock connected to the internal circuitry. XC For applications requiring ±32 ppm clock accuracy, the following requirements should be met. Frequency Tolerance Rise and Fall Time Duty Cycle ZL50015 20 MHz As required Fundamental Parallel Ω ...
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... Characteristics are over recommended operating conditions unless otherwise stated. ‡ Typical figures are at 25°C and are for design aid only: not guaranteed and not subject to production testing. * Note 1: Maximum leakage on pins (output or I/O pins in high impedance state) is over an applied voltage ( ZL50015 Symbol V ...
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... Timing Parameter Measurement Voltage Levels Characteristics 1 CMOS Threshold 2 Rise/Fall Threshold Voltage High 3 Rise/Fall Threshold Voltage Low † Characteristics are over recommended operating conditions unless otherwise stated. ALL SIGNALS Figure 25 - Timing Parameter Measurement Voltage Levels ZL50015 Sym. Level V 0 DD_IO V 0 DD_IO V 0 ...
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... RESET pin is set high. † Characteristics are over recommended operating conditions unless otherwise stated. t CSD CS t DSD DS R/W A0-A13 D0-D15 DTA Figure 26 - Motorola Non-Multiplexed Bus Timing - Read Access ZL50015 Sym Min. Typ. Max CSD t 15 DSD t 0 CSS ...
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... RESET pin is set high. † Characteristics are over recommended operating conditions unless otherwise stated. t CSD CS t DSD DS R/W A0-A13 D0-D15 DTA Figure 27 - Motorola Non-Multiplexed Bus Timing - Write Access ZL50015 Sym. Min. Typ. Max CSD t 15 DSD t 0 CSS ...
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... A delay of 500 µ (see Section 17.2 on page 46) must be applied before the first microprocessor access is Note 2: performed after the RESET pin is set high. † Characteristics are over recommended operating conditions unless otherwise stated A0-A13 D0-D15 RDY Figure 28 - Intel Non-Multiplexed Bus Timing - Read Access ZL50015 Sym. Min. Typ. Max CSD ...
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... A delay of 500 µ (Section 17.2 on page 46) must be applied before the first microprocessor access is performed Note 2: after the RESET pin is set high. † Characteristics are over recommended operating conditions unless otherwise stated A0-A13 D0-D15 RDY Figure 29 - Intel Non-Multiplexed Bus Timing - Write Access ZL50015 Sym. Min. Typ. Max CSD ...
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... AC Electrical Characteristics - OSCi 20 MHz Input Timing Characteristic 1 Input frequency accuracy 2 Duty cycle 3 Input rise or fall time † Characteristics are over recommended operating conditions unless otherwise stated. ‡ See “Performance Characteristics Notes” on page 119. ZL50015 Sym. Min. t 100 TCKP t 20 TCKH t 20 ...
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... CKi Input Clock Rise/Fall Time 8 CKi Input Clock Cycle to Cycle Variation † Characteristics are over recommended operating conditions unless otherwise stated. ‡ Typical figures are at 25°C and are for design aid only: not guaranteed and not subject to production testing. ZL50015 Sym. Min ...
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... FPi t FPIS CKi Input Frame Boundary Figure 31 - Frame Pulse Input and Clock Input Timing Diagram (ST-BUS) FPi t FPIS CKi Input Frame Boundary Figure 32 - Frame Pulse Input and Clock Input Timing Diagram (GCI-Bus) ZL50015 t FPIW t FPIH t CKIP t CKIH t rCKI t FPIW t FPIH t CKIP ...
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... Bit0 Ch31 2.048 Mbps STi0 - 15 Bit0 4.096 Mbps Ch63 STi0 - 15 Bit1 Bit0 Ch127 Ch127 8.192 Mbps Input Frame Boundary Figure 33 - ST-BUS Input Timing Diagram when Operated at 2 Mbps, 4 Mbps, 8 Mbps ZL50015 Sym. Min. Typ. Max SIS2 t 5 SIS4 t 5 SIS8 t ...
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... Ch31 STi0 - 15 Bit7 4.096 Mbps Ch63 STi0 - 15 Bit6 Bit7 Bit0 Ch127 Ch127 Ch0 8.192 Mbps Input Frame Boundary Figure 35 - GCI-Bus Input Timing Diagram when Operated at 2 Mbps, 4 Mbps, 8 Mbps ZL50015 t SIS16 t SIH16 Bit6 Bit5 Bit4 Bit3 Ch0 Ch0 Ch0 Ch0 t SIS2 ...
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... FPi CKi (16.384 MHz) STi0 - 15 Bit6 Bit7 Bit0 Ch255 Ch255 Ch0 16.384 Mbps Input Frame Boundary Figure 36 - GCI-Bus Input Timing Diagram when Operated at 16 Mbps ZL50015 t SIS16 t SIH16 Bit1 Bit2 Bit3 Bit4 Ch0 Ch0 Ch0 Ch0 103 Zarlink Semiconductor Inc. Data Sheet ...
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... Mbps Ch63 STio0 - 15 Bit0 8.192 Mbps Ch127 STio0 - 15 Bit2 Bit1 Bit0 Ch255 Ch255 Ch255 16.384 Mbps Output Frame Boundary Figure 37 - ST-BUS Output Timing Diagram when Operated Mbps ZL50015 Sym. Min. Typ. Max SOD2 SOD4 ...
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... Ch0 t SOD16 STio0 - 15 Bit5 Bit6 Bit7 Bit0 Ch255 Ch255 Ch255 Ch0 16.384 Mbps Output Frame Boundary Figure 38 - GCI-Bus Output Timing Diagram when Operated Mbps ZL50015 t SOD2 Bit0 Ch0 t SOD4 Bit0 Bit1 Ch0 Ch0 SOD8 Bit1 Bit2 Bit3 Bit4 ...
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... pF; high impedance is measured by pulling to the appropriate rail with the time taken to discharge FPo0 CKo0 STio STio Figure 39 - Serial Output and External Control ODE t ZD_ODE STio HiZ ZL50015 Sym. Min. Typ ZD_ODE t ...
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... Characteristics are over recommended operating conditions unless otherwise stated. FPi CKi (16.384 MHz) FPi CKi (8.192 MHz) FPi CKi (4.096 MHz) Input Frame Boundary FPo0 CKo0 (4.096 MHz) Figure 41 - Input and Output Frame Boundary Offset ZL50015 Sym. Min. Typ. Max. t FBOS FBOS FBOS Output Frame Boundary 107 Zarlink Semiconductor Inc ...
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... CKo0 Output Low Time 7 CKo0 Output Rise/Fall Time † Characteristics are over recommended operating conditions unless otherwise stated. ‡ Typical figures are at 25°C and are for design aid only: not guaranteed and not subject to production testing. ZL50015 t FPW0 t FODF0 t CKP0 ...
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... CKo1 Output Low Time 7 CKo1 Output Rise/Fall Time † Characteristics are over recommended operating conditions unless otherwise stated. ‡ Typical figures are at 25°C and are for design aid only: not guaranteed and not subject to production testing. ZL50015 t FPW1 t FODF1 t CKP1 ...
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... CKo2 Output Low Time 7 CKo2 Output Rise/Fall Time † Characteristics are over recommended operating conditions unless otherwise stated. ‡ Typical figures are at 25°C and are for design aid only: not guaranteed and not subject to production testing. ZL50015 t FPW2 t t FODF2 ...
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... CKo3 Output Low Time 7 CKo3 Output Rise/Fall Time † Characteristics are over recommended operating conditions unless otherwise stated. ‡ Typical figures are at 25°C and are for design aid only: not guaranteed and not subject to production testing. ZL50015 t FPW3 t FODF3 t CKP3 ...
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... Characteristics are over recommended operating conditions unless otherwise stated. ‡ Typical figures are at 25°C and are for design aid only: not guaranteed and not subject to production testing. FPo5 (shares output pin with FPo_OFF2) CKo5 Output Frame Boundary Figure 47 - CKo5 Timing Diagram (19.44 MHz) ZL50015 t CKP4 t t CKH4 CKL4 t fCK4 Sym ...
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... CKo5 Output Low Time 7 CKo5 Output Rise/Fall Time † Characteristics are over recommended operating conditions unless otherwise stated. ‡ Typical figures are at 25°C and are for design aid only: not guaranteed and not subject to production testing. ZL50015 Sym. Min. Typ. t ...
Page 114
... REF @ 8 kHz, 2.048, 4.096, 8.192, 16.384 MHz REF @ 1.544 MHz REF @ 19.44 MHz † Characteristics are over recommended operating conditions unless otherwise stated. ‡ See “Performance Characteristics Notes” on page 119. REF0-3 FPo[n] CKo[n] Figure 48 - REF0 - 3 Reference Input/Output Timing ZL50015 Sym. Min RPMIN ...
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... CKo0 to CKo1 (8.192 MHz) delay 2 CKo0 to CKo2 (16.384 MHz) delay 3 CKo0 to CKo3 (32.768 MHz/16.384 MHz/8.192 MHz/4.096 MHz) delay † Characteristics are over recommended operating conditions unless otherwise stated. ‡ See “Performance Characteristics Notes” on page 119. ZL50015 Sym. Min. t C1D t C2D t ...
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... FPo0 CKo0 (4.096 MHz) CKo4 (1.544 MHz) CKo1 (8.192 MHz) CKo2 (16.384 MHz) CKo5 (19.44 MHz) CKo3 (32.768 MHz) Figure 49 - Output Timing (ST-BUS Format) ZL50015 t C4D t C1D t C2D t C5D t C3D 116 Zarlink Semiconductor Inc. Data Sheet ...
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... Normal output phase alignment speed (phase slope Normal phase lock time 1. Reference switching to normal, holdover, or freerun mode 2. -32 to +32 ppm locking † Characteristics are over recommended operating conditions unless otherwise stated. ‡ See “Performance Characteristics Notes” on page 119. ZL50015 Min. Max. -0.003 -0.03 0.03 -260 260 -82 ...
Page 118
... MHz jitter † Characteristics are over recommended operating conditions unless otherwise stated. ‡ Typical figures are at 25°C and are for design aid only: not guaranteed and not subject to production testing. * See “Performance Characteristics Notes” on page 119. ZL50015 ‡ Units Typ. ...
Page 119
... Multi-period near limits and far limits are programmed to +/-64.713ppm & +/-82.487ppm respectively. (ST4_LIM = 1) 13. Multi-period near limits and far limits are programmed to +/-240ppm & +/-250ppm respectively. (ST4_LIM = 0) 14 load on output pin. ZL50015 at 3.3 V and are for design aid only: not guaranteed and not subject to production DD_IO ...
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Zarlink Semiconductor 2003 All rights reserved. 1 ISSUE 214440 ACN 26June03 DATE APPRD. Package Code Previous package codes ...
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Zarlink Semiconductor 2003 All rights reserved. ISSUE ACN DATE APPRD. Package Code Previous package codes ...
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For more information about all Zarlink products Information relating to products and services furnished herein by Zarlink Semiconductor Inc. or its subsidiaries (collectively “Zarlink”) is believed to be reliable. However, Zarlink assumes no liability for errors that may appear in ...