ZL50015 ZARLINK [Zarlink Semiconductor Inc], ZL50015 Datasheet - Page 14

• Manufacturer Part Number: ZL50015
• Description: Enhanced 1 K Digital Switch with Stratum 4E DPLL
• Manufacturer: ZARLINK [Zarlink Semiconductor Inc]

PBGA Pin
B12, B13,
C10, C11,
F13, G4,
Number
C13, G3
K12
M3
G5
K3
L4
L3
LQFP Pin
150, 151,
152, 153,
144, 208
Number
80, 105,
234
238
239
240
212
210
Pin Name
IC_Open
IC_GND
TRST
TMS
TCK
TDo
TDi
Zarlink Semiconductor Inc.
Test Mode Select (5 V-Tolerant Input with Internal Pull-up)
JTAG signal that controls the state transitions of the TAP controller.
This pin is pulled high by an internal pull-up resistor when it is not
driven.
Test Clock (5 V-Tolerant Schmitt-Triggered Input with Internal
Pull-up)
Test Reset (5 V-Tolerant Input with Internal Pull-up)
Asynchronously initializes the JTAG TAP controller by putting it in
the Test-Logic-Reset state. This pin should be pulsed low during
power-up to ensure that the device is in the normal functional
mode. When JTAG is not being used, this pin should be pulled low
during normal operation.
Test Serial Data In (5 V-Tolerant Input with Internal Pull-up)
JTAG serial test instructions and data are shifted in on this pin.
This pin is pulled high by an internal pull-up resistor when it is not
driven.
Test Serial Data Out (5 V-Tolerant Three-state Output)
JTAG serial data is output on this pin on the falling edge of TCK.
This pin is held in high impedance state when JTAG is not
enabled.
Internal Test Mode (5 V-Tolerant Input with Internal Pull-down)
These pins may be left unconnected.
Internal Test Mode Enable (5 V-Tolerant Input)
These pins MUST be low.
Provides the clock to the JTAG test logic.
ZL50015
14
Description
Data Sheet