ZL50015 ZARLINK [Zarlink Semiconductor Inc], ZL50015 Datasheet - Page 46

• Manufacturer Part Number: ZL50015
• Description: Enhanced 1 K Digital Switch with Stratum 4E DPLL
• Manufacturer: ZARLINK [Zarlink Semiconductor Inc]

16.0
The device provides access to the internal registers, connection memories and data memories via the
microprocessor port. The microprocessor port is capable of supporting both Motorola and Intel non-multiplexed
microprocessors. The microprocessor port consists of a 16-bit parallel data bus (D15 - 0), 14 bit address bus (A13 -
0) and six control signals (MOT_INTEL, CS, DS_RD, R/W_WR, IRQ and DTA_RDY).
The data memory can only be read from the microprocessor port. For a data memory read operation, D7 - 0 will be
used and D15 - 8 will output zeros.
For a CM_L read or write operation, all bits (D15 - 0) of the data bus will be used. For a CM_H write operation, D4 -
0 of the data bus must be configured and D15 - 5 are ignored. D15 - 5 must be driven either high or low. For a
CM_H read operation, D4 - 0 will be used and D15 - 5 will output zeros.
Refer to Figure 26 on page 94, Figure 27 on page 95, Figure 28 on page 96 and Figure 29 on page 97 for the
microprocessor timing.
17.0
The RESET pin is used to reset the ZL50015. When this pin is low, the following functions are performed:
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17.1
The recommended power-up sequence is for the V
power-up of the V
as V
17.2
Upon power up, the ZL50015 should be initialized as follows:
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Note: If an external oscillator is used, the waiting time is 500 µs. Without the external oscillator, if CKi is
16.384 MHz, the waiting time is 500 µs; if CKi is 8.192 MHz, the waiting time is 1 ms; if CKi is 4.096 MHz, the
waiting time is 2 ms.
synchronously puts the microprocessor port in a reset state
tristates the STio0 - 15 outputs
drives the STOHZ0 - 7 outputs to high
preloads all internal registers with their default values (refer to the individual registers for default values)
clears all internal counters
Set the ODE pin to low to disable the STio0 - 15 outputs and to drive STOHZ0 - 7 to high
Set the TRST pin to low to disable the JTAG TAP controller
Reset the device by pulsing the RESET pin to zero for longer than 1 µs
After releasing the RESET pin from low to high, wait for a certain period of time (see Note below) for the
device to stabilize from the power down state before the first microprocessor port access can occur
Program CKIN1 - 0 (bit 6 -5) in the Control Register (CR) to define the frequency of the CKi and FPi inputs
Wait at least 500 µs prior to the next microport access (see Note below)
Use the block programming mode to initialize the connection memory
Release the ODE pin from low to high after the connection memory is programmed
DD_IO
Power-up Sequence
Device Initialization on Reset
Microprocessor Port
Device Reset and Initialization
, but should not “lead” the V
DD_CORE
supply (normally +1.8 V). The V
DD_IO
supply by more than 0.3 V.
Zarlink Semiconductor Inc.
ZL50015
DD_IO
46
supply (normally +3.3 V) to be established before the
DD_CORE
supply may be powered up at the same time
Data Sheet