zl50404 Zarlink Semiconductor, zl50404 Datasheet - Page 119
zl50404
Manufacturer Part Number
zl50404
Description
Lightly Managed/unmanaged 5-port 10/100m Ethernet Switch
Manufacturer
Zarlink Semiconductor
Datasheet
1.ZL50404.pdf
(121 pages)
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15.0
15.1
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15.2
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15.3
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15.4
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Initial Release
Updated Ball Signal Description Table :
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Updated Section 1.4 on page 17 to indicate operation of the internal pull up/down resistors in different
modes
Clarified Section 11.1.3 on page 43 on usage of REF_CLK
Clarified PVMODE register bit description for bits [2] & [5]
Updated ECR4Pn register description as port 9 (uplink) operates differently than the RMAC ports for MII
bi-directional clocking (bits [1:0])
I
Added Maximum Junction Temperature to Section 14.1 on page 109
Updated I/O voltage levels to use TTL spec values rather than % of Vcc
Added the following to the Feature List:
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Added section on PHY addresses
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Fixed error in DS on sending Ethernet Frames via serial interface.
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Added more cross-references to available AppNotes
Added more clock descriptions to “Clocks” on page 43
INT_MASK and INTP_MASK registers should state that the default register value is 0x00
Added Errata List to document
Added section on SCL clock generation
Interrupt Register was incorrectly identified as read only, should be read/write
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2
C address mapping was corrected for QOSCn registers
clarified the ball signal I/O description for Mn_TXCLK & Mn_RXCLK showing these signals are either
inputs OR outputs
clarified that M9_MTXCLK is an input only
ball assignments for the Fast Ethernet Access Ports [3:0] MII signals were incorrect
4K jumbo frames
IEEE 802.3ad support
Reverse MII/GPSI
Clarified that they are hard-coded
The Status Bytes is sent before the frame, for both Tx and Rx
Clarified that only bit [7] is not self-clearing
July 2003
November 2003
February 2004
August 2004
Document Errata
Zarlink Semiconductor Inc.
ZL50404
119
Data Sheet
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