zl50404 Zarlink Semiconductor, zl50404 Datasheet - Page 60

• Manufacturer Part Number: zl50404
• Description: Lightly Managed/unmanaged 5-port 10/100m Ethernet Switch
• Manufacturer: Zarlink Semiconductor

13.2
13.2.1
•
•
13.2.2
•
•
13.2.3
•
•
•
13.2.4
•
•
•
Bit [0]:
Bit [1]:
Bit [2]:
Bit [3]:
Bit [4]:
Bit [5]:
Bit [7:6]:
Address for indirectly accessed register addresses (16 bits)
Address = 0 (write only)
Data of indirectly accessed registers (8 bits)
Address = 2 (read/write)
CPU transmit/receive switch frames (16 bits)
Address = 3 (read/write)
Format:
CPU interface commands and status (8 bits)
Address = 4 (read/write)
When the CPU writes to this register
Directly Accessed Registers
INDEX_REG0
DATA_FRAME_REG
CONTROL_FRAME_REG
COMMAND&STATUS Register
8-byte of Frame status (Frame size, Source port #, VLAN tag)
Frame Data (size should be in multiple of 8-byte)
Set Control Frame Receive buffer ready, after CPU writes a complete frame into the buffer. This
bit is self-cleared.
Set Control Frame Transmit buffer1 ready, after CPU reads out a complete frame from the buffer.
This bit is self-cleared.
Set Control Frame Transmit buffer2 ready, after CPU reads out a complete frame from the buffer.
This bit is self-cleared.
Set this bit to indicate CPU received a whole frame (transmit FIFO frame receive done), and
flushed the rest of frame fragment, If occurs. This bit will be self-cleared.
Set this bit to indicate that the following Write to the Receive FIFO is the last one (EOF). This bit
will be self-cleared.
Set this bit to re-start the data that is sent from the CPU to Receive FIFO (re-align). This feature
can be used for software debug. For normal operation must be '0'.
Reserved. Must be '0'
Zarlink Semiconductor Inc.
ZL50404
60
Data Sheet