zl50418 Zarlink Semiconductor, zl50418 Datasheet - Page 111

• Manufacturer Part Number: zl50418
• Description: Managed 16-port 10/100 M + 2-port 1 G Ethernet Switch
• Manufacturer: Zarlink Semiconductor

14.12.7
CPU Address: hF07
Accessed by serial interface (RW)
The OE_CLK is used for generating the OE0 and OE1 signals.
PD[15:13]
000b
001b
010b
011b
100b
101b
110b
111b
14.12.8
CPU Address: hFFF
Accessed by CPU and serial interface (RO)
Always return 8’h DA . Indicate the CPU interface or serial port connection is good.
14.13
Two sets of TBI registers are used for configure the two Gigabit ports if they are operating in TBI mode. These TBI
registers are located inside the switching chip and they are accessed through the MII command and MII data
registers.
14.13.1
MII Address: h00
Read/Write
TBI Registers
Bit [15]
Bit [14]
Bit [13]
Bit [12]
Bit [11:10]
OECLK - Internal OE_CLK delay from SCLK
DA – DA Register
Control Register
OECLK
01h
10h
02h
80h
40h
20h
08h
04h
Delay
Reset PCS logic and all TBI registers
1 = Reset.
0 = Normal operation.
Reserved. Must be programmed with “0”.
Speed selection (See bit 6 for complete details)
Auto Negotiation Enable
1 = Enable auto-negotiation process.
0 = Disable auto-negotiation process (Default).
Reserved. Must be programmed with “0”
1 Buffers Delay
5 Buffers Delay
2 Buffers Delay
8 Buffers Delay
7 Buffers Delay (Recommend)
6 Buffers Delay
4 Buffers Delay
3 Buffers Delay
Zarlink Semiconductor Inc.
ZL50418
111
Data Sheet