zl50417 ETC-unknow, zl50417 Datasheet
zl50417
Related parts for zl50417
zl50417 Summary of contents
Page 1
... SRAM (1M/ 2M) FDB Interface Search Frame Engine Engine GMII/ GMII/ Management PCS PCS RMII Port Port Module 0 1 Figure 1 - System Block Diagram ZL50417 2-Port 1G Ethernet Switch Data Sheet February 2003 Ordering Information ZL50417/GKC 553 PIN HSBGA - +85 C LED MCT Link 1 ...
Page 2
... Gigabit port) and 2 levels of dropping precedence. Each packet is assigned a transmission priority and dropping precedence based on the VLAN priority field in a VLAN tagged frame, or the DS/TOS field, and UDP/TCP logical port fields in IP packets. The ZL50417 recognizes a total of 16 UDP/TCP logical ports, 8 hard-wired and 8 programmable (including one programmable range). ...
Page 3
... Start Condition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15 2.2.2 Address .15 2.2.3 Data Direction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15 2.2.4 Acknowledgment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15 2.2.5 Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15 2.2.6 Stop Condition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15 2.3 Synchronous Serial Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16 2.3.1 Write Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16 2.3.2 Read Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16 3.0 ZL50417 Data Forwarding Protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17 3.1 Unicast Data Frame Forwarding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17 3.2 Multicast Data Frame Forwarding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17 4.0 Memory Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18 4.1 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18 4.2 Detailed Memory Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18 4.3 Memory Requirements .19 5.0 Search Engine .20 5.1 Search Engine Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20 5 ...
Page 4
... SCAN LINK and SCAN COL interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 12.0 LED Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 12.1 LED Interface Introduction 12.2 Port Status 12.3 LED Interface Timing Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 13.0 Register Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 13.1 ZL50417 Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 13.2 (Group 0 Address) MAC Ports Group . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 13.2.1 ECR1Pn: Port N Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 13.2.2 ECR2Pn: Port N Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 13.2.3 GGControl – Extra GIGA Port Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 13.3 (Group 1 Address) VLAN Group . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 13.3.1 AVTCL – ...
Page 5
... USER_PORT_[5:4]_PRIORITY - User Define Logic Port 5 and 4 Priority . . . . . . . . . . . . .71 13.7.40.5 USER_PORT_[7:6]_PRIORITY - User Define Logic Port 7 and 6 Priority . . . . . . . . . . . . .71 13.7.40.6 USER_PORT_ENABLE[7:0] – User Define Logic Port Enables .71 13.7.40.7 WELL_KNOWN_PORT[1:0] PRIORITY- Well Known Logic Port 1 and 0 Priority . . . . . . .72 13.7.40.8 WELL_KNOWN_PORT[3:2] PRIORITY- Well Known Logic Port 3 and 2 Priority . . . . . . .72 Table of Contents Zarlink Semiconductor Inc. ZL50417 5 ...
Page 6
... ZL50417 13.7.40.9 WELL_KNOWN_PORT [5:4] PRIORITY- Well Known Logic Port 5 and 4 Priority . . . . . . 72 13.7.40.10 WELL_KNOWN_PORT [7:6] PRIORITY- Well Known Logic Port 7 and 6 Priority . . . . . 72 13.7.40.11 WELL KNOWN_PORT_ENABLE [7:0] – Well Known Logic Port Enables 13.7.40.12 RLOWL – User Define Range Low Bit 7 13.7.40.13 1RLOWH – User Define Range Low Bit 15: 13.7.40.14 RHIGHL – User Define Range High Bit 7 13.7.40.15 RHIGHH – ...
Page 7
... Reduced Media Independent Interface .108 14.7.2 Gigabit Media Independent Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .109 14.7.3 LED Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .113 14.7.4 SCANLINK SCANCOL Output Delay Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .114 14.7.5 MDIO Input Setup and Hold Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .115 14.7.6 I²C Input Setup Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .116 14.7.7 Serial Interface Setup Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .117 Table of Contents Zarlink Semiconductor Inc. ZL50417 7 ...
Page 8
... ZL50417 8 Zarlink Semiconductor Inc. Data Sheet ...
Page 9
... Table 4 - Four QoS Configurations for a 10/100 Mbps Port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 Table 5 - Four QoS Configurations for a Gigabit Port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 Table 6 - Mapping between ZL50417 and IETF Diffserv Classes for Gigabit Ports . . . . . . . . . . . . . . . . . . . . . . . . 34 Table 7 - Mapping between ZL50417 and IETF Diffserv Classes for 10/100 Ports . . . . . . . . . . . . . . . . . . . . . . . . 35 Table 8 - ZL50417 Features Enabling IETF Diffserv Standards . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 Table 9 - Select via trunk0_mode register ...
Page 10
... ZL50417 10 Zarlink Semiconductor Inc. Data Sheet ...
Page 11
... Figure 1 - System Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Figure 2 - Data Transfer Format for I2C Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Figure 3 - Write Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Figure 4 - Read Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Figure 5 - ZL50417 SRAM Interface Block Diagram (DMAs for 10/1000 Ports Only Figure 6 - Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Figure 7 - Priority Classification Rule . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 Figure 8 - Memory Configuration For: 2 banks, 1 Layer, 2MB total . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 Figure 9 - Memory Configuration For: 2 banks, 2 Layers, 4MB total ...
Page 12
... ZL50417 12 Zarlink Semiconductor Inc. Data Sheet ...
Page 13
... The ZL50417 GMAC implements both GMII and MII interface, which offers a simple migration from 10/100 to 1G. The GMAC of the ZL50417 meets the IEEE 802.3Z specification able to operate in 10M/100M either Half or Full Duplex mode with a back pressure/flow control mechanism Full duplex mode with flow control mechanism ...
Page 14
... Engine (FE) and the external physical device (PHY). The ZL50417 has two interfaces, RMII or Serial (only for 10M). The 10/100 MAC of the ZL50417 device meets the IEEE 802.3 specification able to operate in either Half or Full Duplex mode with a back pressure/flow control mechanism. In addition, it will automatically retransmit upon collision for total transmissions ...
Page 15
... Start Condition Generated by the master (in our case, the ZL50417). The bus is considered to be busy after the Start condition is generated. The Start condition occurs if while the SCL line is High, there is a High-to-Low transition of the SDA line. Other than in the Start condition (and Stop condition), the data on the SDA line must be stable during the High period of SCL. The High or Low state of SDA can only change when SCL is Low. In addition, when the I² ...
Page 16
... Synchronous Serial Interface The synchronous serial interface serves the function of configuring the ZL50417 not at boot time but via a PC. The PC serves as master and the ZL50417 serves as slave. The protocol for the synchronous serial interface is nearly identical to the I²C protocol. The main difference is that there is no acknowledgment bit after each byte of data transferred ...
Page 17
... Data Sheet All registers in ZL50417 can be modified through this synchronous serial interface. 3.0 ZL50417 Data Forwarding Protocol 3.1 Unicast Data Frame Forwarding When a frame arrives assigned a handle in memory by the Frame Control Buffer Manager (FCB Manager). An FCB handle will always be available, because of advance buffer reservations. ...
Page 18
... Memory Interface 4.1 Overview The ZL50417 provides two 64-bit-wide SRAM banks, SRAM Bank A and SRAM Bank B, with a 64-bit bus connected to each. Each DMA can read and write from both bank A and bank B. The following figure provides an overview of the ZL50417 SRAM banks. SRAM Bank A ...
Page 19
... Frame Buffer VLAN Disable 1K Enable 1K Disable 2K Enable 2K Frame Data Buffer (FDR) Area MAC Address Control Table (MCT) Area VLAN Table Area Figure 6 - Memory Map Zarlink Semiconductor Inc. Max MAC Address 32K 31.5K 64K 63.5K 2M Bank A 2M Bank B 1.5M 1.5M 0.5M 0.5M 2M Bank A 2M Bank B 1.5M 1.5M 0.5M – ZL50417 19 ...
Page 20
... Basic Flow Shortly after a frame enters the ZL50417 and is written to the Frame Data Buffer (FDB), the frame engine generates a Switch Request, which is sent to the search engine. The switch request consists of the first 64 bytes of the frame, which contain all the necessary information for the search engine to perform its task. When the search engine is done, it writes to the Switch Response Queue, and the frame engine uses the information provided in that queue for scheduling and forwarding ...
Page 21
... Extensive core QoS mechanisms are built into the ZL50417 architecture to ensure policy enforcement and buffering of the ingress port, as well as weighted fair-queue(WFQ) scheduling at the egress port. In the ZL50417, QoS-based policies sort traffic into a small number of classes and mark the packets accordingly. The QoS identifier provides specific treatment to traffic in different classes, so that different quality of service is provided to each class ...
Page 22
... In a logical port-based set up, a logical port provides the application information of the packet. Certain applications are more sensitive to delays than others; using logical ports to classify packets can help speed up delay sensitive applications, such as VoIP. 5.5 Priority Classification Rule Figure 7 shows the ZL50417 priority classification rule. 22 Figure 7 - Priority Classification Rule Zarlink Semiconductor Inc. Data Sheet ...
Page 23
... Definition” on page 42). For example, ports 1-3 might be assigned to the Marketing VLAN, ports 4-6 to the Engineering VLAN, and ports 7-9 to the Administrative VLAN. The ZL50417 determines the VLAN membership of each packet by noting the port on which it arrives. From there, the ZL50417 determines which outgoing port(s) is/are eligible to transmit each packet, or whether the packet should be discarded. ...
Page 24
... ZL50417 5.7 Memory Configurations The ZL50417 supports the following memory configurations. Pipeline SBRAM modes support 1 M and 2M per bank configurations. For detail connection information, please reference the memory application note. Configuration Single Layer Two 128 (Bootstrap pin SRAM/bank TSTOUT13 = open) or One 128 SRAM/bank ...
Page 25
... Data LB_D[63:32] Data LB_D[31:0] SRAM SRAM Memory Memory 128 K 128 K 32 bits 32 bits SRAM SRAM Memory Memory 128 K 128 K 32 bits 32 bits Address LB_A[19:3] Zarlink Semiconductor Inc. ZL50417 Memory 128 K 32 bits SRAM Memory 128 K 32 bits SRAM Memory 128 K 32 bits 25 ...
Page 26
... ZL50417 BANK A (2M One Layer) Data LA_D[63:32] Data LA_D[31:0] SRAM Memory 256 K 32 bits Address LA_A[20:3] Bootstraps: TSTOUT7 = Pull Down, TSTOUT13 = Open, TSTOUT4 = Open Figure 10 - Memory Configuration For: 2 banks, 1 Layer, 4MB Total 6.0 Frame Engine 6.1 Data Forwarding Summary When a frame enters the device at the RxMAC, the RxDMA will move the data from the MAC RxFIFO to the FDB. ...
Page 27
... Data Sheet 6.2 Frame Engine Details This section briefly describes the functions of each of the modules of the ZL50417 frame engine. 6.2.1 FCB Manager The FCB manager allocates FCB handles to incoming frames, and releases FCB handles upon frame departure. The FCB manager is also responsible for enforcing buffer reservations and limits. The default values can be determined by referring to Chapter 7 ...
Page 28
... ZL50417 7.0 Quality of Service and Flow Control 7.1 Model Quality of service is an all-encompassing term for which different people have different interpretations. In general, the approach to quality of service described here assumes that we do not know the offered traffic pattern. We also assume that the incoming traffic is not policed or shaped. Furthermore, we assume that the network manager knows his applications, such as voice, file transfer, or web browsing, and their relative importance ...
Page 29
... It is also possible to add a fourth class that has strict priority over the other three; if this class has even one frame to transmit, then it goes first. In the ZL50417, each 10/100 Mbps port will support four total classes, and each 1000 Mbps port will support eight classes. We will discuss the various modes of scheduling these classes in the next section ...
Page 30
... P3 traffic is very light and predictably patterned). Strict priority traffic, if not admission-controlled at a prior stage to the ZL50417, can have an adverse effect on all other classes’ performance. For a 1 Gbps port, P7 and P6 are both SP classes, and P7 has strict priority over P6. In this case, the delay bounds per class are 0.32 ms for P5, 0 ...
Page 31
... This provides per-class bandwidth partitioning with error within 2%. In WFQ mode, though we do not assure frame latency, the ZL50417 still retains a set of dropping rules that helps to prevent congestion and trigger higher level protocol end-to-end flow control. ...
Page 32
... Such a temporary region is necessary, because when the frame first enters the ZL50417, its destination port and class are as yet unknown, and so the decision to drop or not needs to be temporarily postponed. This ensures that every frame can be received first before subjecting them to the frame drop discipline after classifying ...
Page 33
... ZL50417 Flow Control Basics Because frame loss is unacceptable for some applications, the ZL50417 provides a flow control option. When flow control is enabled, scarcity of buffer space in the switch may trigger a flow control signal; this signal tells a source port that is sending a packet to this switch, to temporarily hold off. ...
Page 34
... Xon is triggered when a port is currently being flow controlled, and all of that port’s reserved FDB slots have been released. Note that the ZL50417’s per-source-port FDB reservations assure that a source port that sends a single frame to a congested destination will not be flow controlled. ...
Page 35
... BE class. ZL504xx IETF Table 7 - Mapping between ZL50417 and IETF Diffserv Classes for 10/100 Ports Features of the ZL50417 that correspond to the requirements of their associated IETF classes are summarized in the table below. Network management (NM) and Expedited forwarding (EF) Assured forwarding (AF) ...
Page 36
... ZL50417 The ZL50417 also provides a safe fail-over mode for port trunking automatically. If one of the ports in the trunking group goes down, the ZL50417 will automatically redistribute the traffic over to the remaining ports in the trunk. 8.2 Unicast Packet Forwarding The search engine finds the destination MCT entry, and if the status field says that the destination port found belongs to a trunk, then the group number is retrieved instead of the port number. In addition, if the source address belongs to a trunk, then the source port’ ...
Page 37
... Port Mirroring 9.1 Port Mirroring Features The received or transmitted data of any 10/100 port in the ZL50417 chip can be “mirrored” to any other port. We support two such mirrored source-destination pairs. A mirror port can not also serve as a data port. 9.2 Setting Registers for Port Mirroring MIRROR1_SRC: Sets the source port for the first port mirroring pair ...
Page 38
... The TBI interface can be used for 1000Mbps fiber operation. In this mode, the ZL50417 is connected to the Serdes as shown in Figure 13. There are two TBI interfaces in the ZL50417 devices. To enable to TBI function, the corresponding TXEN and TXER pins need to be boot strapped. See Ball – Signal Description for details. ...
Page 39
... The GPSI interface can be operated in port based VLAN mode only. CRS_DV RXD[0] RXD[1] TXD[1] TXD[0] 5041X Figure 14 - GPSI (7WS) mode connection diagram crs rxd rx_clk tx_clk txd TXEN txen Zarlink Semiconductor Inc. ZL50417 Port 0 link0 Ethernet col0 PHY link1 col1 link2 col2 link15 col15 Port 15 Ethernet PHY Link ...
Page 40
... A low cost external device (44 pin PAL) is used to decode the serial data and to drive an LED array for display. This device can be customized for different needs. 12.2 Port Status In the ZL50417, each port has 8 status indicators, each represented by a single bit. The 8 LED status indicators are: - Bit 0: Flow control ...
Page 41
... G0 port (1= port 24 is operating at Gigabit speed; 0= speed is either 10 or 100 Mb/s depending on speed bit of Port 24) - 26[1]: G1 port (1= port 25 is operating at Gigabit speed; 0= speed is either 10 or 100 Mb/s depending on speed bit of Port 25) - 26[2]: initialization done - 26[3]: initialization start - 26[4]: checksum ok - 26[5]: link_init_complete - 26[6]: bist_fail - 26[7]: ram_error - 27[0]: bist_in_process - 27[1]: bist_done Zarlink Semiconductor Inc. ZL50417 41 ...
Page 42
... ZL50417 12.3 LED Interface Timing Diagram The signal from the ZL50417 to the LED decoder is shown in Figure 16. 42 Figure 16 - Timing Diagram of LED Interface Zarlink Semiconductor Inc. Data Sheet . ...
Page 43
... Data Sheet 13.0 Register Definition 13.1 ZL50417 Register Description Register 0. ETHERNET Port Control Registers Substitute [N] with Port number (0..F, 18-1A) ECR1P”N” Port Control Register 1 for Port N ECR2P”N” Port Control Register 2 for Port N GGC Extra GIGA bit control register 1. VLAN Control Registers Substitute [N] with Port number (0..F, 18-1A) ...
Page 44
... ZL50417 Register FCR Flooding Control Register AVPML VLAN Priority Map Low AVPMM VLAN Priority Map Middle AVPMH VLAN Priority Map High TOSPML TOS Priority Map Low TOSPMM TOS Priority Map Middle TOSPMH TOS Priority Map High AVDM VLAN Discard Map TOSDML ...
Page 45
... Zarlink Semiconductor Inc. ZL50417 I²C R/W Addr Default Notes (Hex) R/W 0FC 088 R/W 0D6- 000 0DD R/W 0DE- 000 0E5 R/W 0E6 000 R/W 0E7 ...
Page 46
... ZL50417 Register FEN Feature Registers MIIC0 MII Command Register 0 MIIC1 MII Command Register 1 MIIC2 MII Command Register 2 MIIC3 MII Command Register 3 MIID0 MII Data Register 0 MIID1 MII Data Register 1 LED LED Control Register SUM EEPROM Checksum Register 7. Port Mirroring Controls MIRROR1_SRC ...
Page 47
... Enable Asymmetric flow control • When this bit is set, and flow control is on (bit[0] = 0), don’t send out a flow control frame. But MAC receiver interprets and processes flow control frames A-FC Port Mode Zarlink Semiconductor Inc. ZL50417 ...
Page 48
... WFQ credit set 3 Bit[7:6] • Security Enable (Default 00). The ZL50417 checks the incoming data for one of the following conditions: • If the source MAC address of the incoming packet is in the MAC table and is defined as secure address but the ingress port is not the same as the port associated with the MAC address in the MAC table ...
Page 49
... A MAC address is defined as secure when its entry at MAC table has static status and bit 0 is set to 1. MAC address bit 0 (the first bit transmitted) indicates whether the address is unicast or multicast. As source addresses are always unicast bit 0 is not used (always 0). ZL50417 uses this bit to define secure MAC addresses. • ...
Page 50
... Gigabit port operates at 10/100 mode Bit[6]: • Reserved - Must be zero Bit[7]: • GIGA port B direct flow control (MAC to MAC connection). ZL50417 supports direct flow control mechanism; the flow control frame is therefore not sent through the Gigabit port data path Direct flow control disabled (default Direct flow control enabled 13 ...
Page 51
... Disable fix priority. All frames are analyzed. Transmit Priority and Discard Priority are based on VLAN Tag, TOS or Logical Port. • 1 Transmit Priority and Discard Priority are based on values programmed in bit [6: Drop Default tx priority VLAN Mask Zarlink Semiconductor Inc. ZL50417 0 51 ...
Page 52
... ZL50417 13.4 Port Configuration Registers PVMAP01_0,1,3 I²C Address h3C,3D,3E,3F; CPU Address:h106,107,108,109) PVMAP02_0,1,3 I²C Address h40,41,42,43; CPU Address:h10A, 10B, 10C, 10D) PVMAP03_0,1,3 I²C Address h44,45,46,47; CPU Address:h10E, 10F, 110, 111) PVMAP04_0,1,3 I²C Address h48,49,4A,4B; CPU Address:h112, 113, 114, 115) PVMAP05_0,1,3 I²C Address h4C,4D,4E,4F; CPU Address:h116, 117, 118, 119) PVMAP06_0,1,3 I² ...
Page 53
... Use source destination MAC address and ingress physical port number for hashing 13.5.2 TRUNK1_MODE – Trunk group 1 mode I²C Address h0A6; CPU Address:20B Accessed by serial interface and I²C (R/ Hash Port Select Select Port Select Zarlink Semiconductor Inc. ZL50417 0 53 ...
Page 54
... ZL50417 Bit [1:0]: • Port selection in unmanaged mode. Input pin TRUNK1 enable/disable trunk group 1 in unmanaged mode Trunk Group 2 13.5.3 TRUNK2_MODE – Trunk group 2 mode (Gigabit ports 1 and 2) CPU Address:210 Accessed by serial interface (R/W) 7 Bit [3:0] • Bit [6:4] • • • • • 13.5.4 RQSS – Receive Queue Status ...
Page 55
... SL DMS 1 – Disable speedup aging when MCT resource is low. 0 – Enable speedup aging when MCT resource is low. 1– Enable slow learning. Learning is temporary disabled when search demand is high 0 – Learning is performed independent of search demand Zarlink Semiconductor Inc. ZL50417 0 55 ...
Page 56
... ZL50417 13.7 (Group 5 Address) Buffer Control/QOS Group 13.7.1 FCBAT – FCB Aging Timer I²C Address h0AA; CPU Address:h500 7 Bit [7:0]: • FCB Aging time. Unit of 1ms. (Default FF) • This is for buffer aging control used to configure the buffer aging time. This function can be enabled/disabled through bootstrap pin not suggested to use this function for normal operation ...
Page 57
... This feature allows the user the flexibility of redefining the VLAN priority field. For example, programming a value of 7 into bit 2:0 of the AVPML register would map VLAN priority 0 into internal transmit priority 7. The new priority is used inside the ZL50417. When the packet goes out it carries the original priority. ...
Page 58
... ZL50417 13.7.5 AVPMM – VLAN Priority Map I²C Address h0AE, CPU Address:h504 Accessed by serial interface and I²C (R/W) Map VLAN priority into eight level transmit priorities: 7 VP5 Bit [0]: Priority when the VLAN tag priority field is 2 (Default 0) Bit [3:1]: Priority when the VLAN tag priority field is 3 (Default 0) ...
Page 59
... Frame drop priority when VLAN Tag priority field is 3 (Default 0) Bit [4]: Frame drop priority when VLAN Tag priority field is 4 (Default TP4 5 4 TP7 TP6 FDV6 FDV5 FDV4 FDV3 Zarlink Semiconductor Inc TP3 TP2 2 0 TP5 FDV2 FDV1 FDV0 ZL50417 59 ...
Page 60
... ZL50417 Bit [5]: Frame drop priority when VLAN Tag priority field is 5 (Default 0) Bit [6]: Frame drop priority when VLAN Tag priority field is 6 (Default 0) Bit [7]: Frame drop priority when VLAN Tag priority field is 7 (Default 0) 13.7.11 TOSDML – TOS Discard Map I²C Address h0B4, CPU Address:h50A Accessed by serial interface and I² ...
Page 61
... PR100[7:4] level. Also the threshold for initiating UC flow control. • Default Unicast congest threshold 5 4 Multicast congest threshold Buffer reservation h36 for 16+2 configuration with memory 2MB/bank; h24 for 16+2 configuration with 1MB/bank; Zarlink Semiconductor Inc. ZL50417 ...
Page 62
... ZL50417 13.7.16 PRG – Port Reservation for Giga ports I²C Address h0B9, CPU Address 50F Accessed by serial interface and I²C (R/W) 7 Buffer low threshold Bit [3:0]: Per source port buffer reservation. Define the space in the FDB reserved for each Gigabit port. Expressed in multiples of 16 packets. For each packet 1536 bytes are reserved in the memory ...
Page 63
... Class 5 FCB Reservation Buffer reservation for class 5. Granularity 1. (Default 0) 13.7.22 C6RS – Class 6 Reserve Size I²C Address h0BF; CPU Address 515 Accessed by serial interface and I²C (R/W) 7 Class 6 FCB Reservation Buffer reservation for class 6 (second highest priority). Granularity 1. (Default 0) Zarlink Semiconductor Inc. ZL50417 ...
Page 64
... ZL50417 13.7.23 C7RS – Class 7 Reserve Size I²C Address h0C0; CPU Address 516 Accessed by serial interface and I²C (R/W) 7 Class 7 FCB Reservation Buffer reservation for class 7 (highest priority). Granularity 1. (Default 0) 13.7.24 QOSCn - Classes Byte Limit Set 0 Accessed by serial interface and I²C (R/W): C — QOSC00 – BYTE_C01 (I²C Address h0C1, CPU Address 517) B — ...
Page 65
... B - QOSC22 – BYTE_C6_G2 (I²C Address h0D1, CPU Address 52d QOSC23 – BYTE_C7_G2 (I²C Address h0D2, CPU Address 52e) QOSC12 through QOSC17 represent the values A-F for Gigabit port 2. They are per-queue byte thresholds for random early drop. QOSC17 represents A, and QOSC12 represents F. Zarlink Semiconductor Inc. ZL50417 65 ...
Page 66
... ZL50417 Granularity when Delay bound is used: QOSC17 and QOSC16: 256 bytes, QOSC15 and QOSC14: 512 bytes, QOSC13 and QOSC12: 1024 bytes. Granularity when WFQ is used: QOSC17 to QOSC12: 1024 bytes 13.7.30 Classes WFQ Credit Set 0 Accessed by serial interface W3 - QOSC24[5:0] – CREDIT_C00 (CPU Address 52f QOSC25[5:0] – ...
Page 67
... W1 - QOSC46[5:0] – CREDIT_C6_G1 (CPU Address 545 QOSC47[5:0] – CREDIT_C7_G1 (CPU Address 546) QOSC40 through QOSC47 represents the set of WFQ parameters for Gigabit port 24. The granularity of the numbers is 1, and their sum must be 64. QOSC47 corresponds to W0, and QOSC40 corresponds to W7. Zarlink Semiconductor Inc. ZL50417 67 ...
Page 68
... ZL50417 13.7.35 Classes WFQ Credit Port G2 Accessed by serial interface W7 - QOSC48[5:0] – CREDIT_C0_G2(CPU Address 547) [7:6]: Priority service type. Option QOSC49[5:0] – CREDIT_C1_G2(CPU Address 548) [7]: Priority service allow flow control for the ports select this parameter set. [6]: Flow control pause best effort traffic only W5 - QOSC50[5:0] – ...
Page 69
... See Programming QoS Registers application note for more information 13.7.40 User Defined Logical Ports and Well Known Ports The ZL50417 supports classifying packet priority through layer 4 logical port information. It can be setup by 8 Well Known Ports, 8 User Defined Logical Ports, and 1 User Defined Range. The 8 Well Known Ports supported are: • ...
Page 70
... ZL50417 registers. Two registers are required to be programmed for the logical port number. The respective priority can be programmed to the User_Port [7:0] priority register. The port priority can be individually enabled/disabled via User_Port_Enable register. The User Defined Range provides a range of logical port numbers with the same priority level. Programming is similar to the User Defined Logical Port ...
Page 71
... I²C Address h0EA, CPU Address 594 Accessed by serial interface and I²C (R/ (Default 00 Priority 3 Drop Priority Priority 5 Drop Priority Priority 7 Drop Priority Zarlink Semiconductor Inc. ZL50417 1 0 Drop 1 0 Drop 1 0 Drop ...
Page 72
... ZL50417 13.7.40.7 WELL_KNOWN_PORT[1:0] PRIORITY- Well Known Logic Port 1 and 0 Priority I²C Address h0EB, CPU Address 595 Accessed by serial interface and I²C (R/W) Priority 0 - Well known port 23 for telnet applications. Priority 1 - Well Known port 512 for TCP/UDP. (Default 00) 13.7.40.8 WELL_KNOWN_PORT[3:2] PRIORITY- Well Known Logic Port 3 and 2 Priority I² ...
Page 73
... I²C Address h0D4, CPU Address: 59d Accessed by serial interface and I²C (R/W) (Default 00) 13.7.40.16 RPRIORITY – User Define Range Priority I²C Address h0D5, CPU Address: 59e Accessed by serial interface and I²C (R/ Range Transmit Priority Zarlink Semiconductor Inc. ZL50417 Drop 73 ...
Page 74
... ZL50417 RLOW and RHIGH form a range for logical ports to be classified with priority specified in RPRIORITY. Bit[3:1] Transmit Priority Bits[0]: Drop Priority 13.8 (Group 6 Address) MISC Group 13.8.1 MII_OP0 – MII Register Option 0 I²C Address F0, CPU Address:h600 Accessed by serial interface and I²C (R/W) 7 hfc ...
Page 75
... Note: Before programming MII command: set FEN[6], check MIIC3, making sure no RDY and no VALID; then program MII command Mii 0 – Disable 1 – Enable (all ports) 0: Enable MII Management State Machine 1: Disable MII Management State Machine 0 – Enable using MCT Link structure 1 - Disable using MCT Link List structure Zarlink Semiconductor Inc ZL50417 75 ...
Page 76
... ZL50417 13.8.6 MIIC2 – MII Command Register 2 CPU Address:h605 Accessed by serial interface only (R/ Bit [4:0] REG_AD – Register PHY Address - Bit [6:5] OP – Operation code “10” for read command and “01” for write command Note: Before programming MII command: set FEN[6], check MIIC3, making sure no RDY and no VALID; then program MII command ...
Page 77
... The checksum formula is: FF I²C register = When the ZL50417 boots from the EEPROM the checksum is calculated and the value must be zero. If the checksum is not zeroed the ZL50417 does not start and pin CHECKSUM_OK is set to zero ...
Page 78
... ZL50417 13.9 (Group 7 Address) Port Mirroring Group 13.9.1 MIRROR1_SRC – Port Mirror source port CPU Address 700 Accessed by serial interface (R/W) (Default 7F Bit [4:0]: Source port to be mirrored. Use illegal port number to disable mirroring - Bit [5]: 1 – select ingress data 0 – select egress data ...
Page 79
... Busy writing configuration to I²C 0: Not busy (not writing configuration to I²C) Bit[1]: 1: Busy reading configuration from I²C 0: Not busy (not reading configuration from I² Dest Port Select Reset Bist Signature RE BinP Zarlink Semiconductor Inc. ZL50417 ...
Page 80
... ZL50417 Bit[2]: 1: BIST in progress 0: BIST not running Bit[3]: 1: RAM Error 0: RAM OK Bit[5:4]: Device Signature 11: ZL50417 device Bit [7:6]: Revision 00: Initial Silicon 01: XA1 Silicon 10: Production Silicon 13.10.3 DCR1-Giga port status CPU Address: hF02 Accessed by serial interface. (RO) 7 CIC Bit [1:0]: Giga port 0 strap option - - - ...
Page 81
... Reserved 5’b10010 - Reserved 5’b00011 - Reserved 5’b10100 - Reserved 5’b10101 - Reserved 5’b10110 - Reserved 5’b10111 - Reserved 5’b11000 - Reserved 5’b11001 - Port 25 Operating mode/Neg status (Gigabit 1) 5’b11010 - Port 26 Operating mode/Neg status (Gigabit Sig Giga Inkdn Zarlink Semiconductor Inc Fdpx FcEn ZL50417 81 ...
Page 82
... ZL50417 When bit is 1: Bit[0] – Flow control enable Bit[1] – Full duplex port Bit[2] – Fast Ethernet port (if not gigabit port) Bit[3] – Link is down Bit[4] – Giga port Bit[5] – Signal detect (when PCS interface mode) Bit[6] - reserved Bit[7] – Module detected (for hot swap purpose) 13 ...
Page 83
... Speed selection (See bit 6 for complete details) Bit [12] Auto Negotiation Enable 1 = Enable auto-negotiation process Disable auto-negotiation process (Default). Bit [11:10] Reserved. Must be programmed with “0” 8 Buffers Delay 7 Buffers Delay (Recommend) 6 Buffers Delay 5 Buffers Delay 4 Buffers Delay 3 Buffers Delay 2 Buffers Delay 1 Buffers Delay Zarlink Semiconductor Inc. ZL50417 83 ...
Page 84
... ZL50417 Bit [9] Restart Auto Negotiation Restart auto-negotiation process Normal operation (Default). Bit [8:7] Reserved. Bit [6] Speed Selection Bit[6][13 Reserved 0 =1000Mb/s (Default) 1 =100Mb =10Mb/s Bit [5:0] Reserved. Must be programmed with “0”. 13.11.2 Status Register MII Address: h01 Read Only Bit [15:9] Reserved. Always read back as “0”. ...
Page 85
... Reserved. Always read back as “0”. Bit [8:7] Pause. Bit [6] Half Duplex 1 = Support half duplex not support half duplex. Bit [5] Full duplex 1 = Support full duplex not support full duplex. Bit [4:0] Reserved. Always read back as “0”. Zarlink Semiconductor Inc. ZL50417 85 ...
Page 86
... ZL50417 13.11.5 Expansion Register MII Address: h06 Read Only Bit [15:2] Reserved. Always read back as “0”. Bit [1] Page Received new page has been received new page has not been received. Bit [0] Reserved. Always read back as “0”. 13.11.6 Extended Status Register ...
Page 87
... ZL50417 ...
Page 88
... ZL50417 14.2 Power and Ground Distribution The following figure provides an encapsulated view of the power and ground distribution ...
Page 89
... Output Output with pull up Output with pull up Output with pull up Output with pull up Output with pull up Zarlink Semiconductor Inc. ZL50417 Description I²C Data Clock I²C Data I/O Serial Strobe Pin Serial Data Input Serial Data Output (AutoFD) Frame Bank A– Data Bit [63:0] Frame Bank A – ...
Page 90
... ZL50417 Ball No(s) C8 LA_OE# A9 LA_OE0# B9 LA_OE1# F4, F5, G4, G5, H4, H5, LB_D[63:0] J4, J5, K4, K5, L4, L5, M4, M5, N4, N5, G3, H1, H2, H3, J1, J2, J3, K1, K2, K3, L1, L2, L3, M1, M2, M3, U4, U5, V4, V5, W4, W5, Y4, Y5, AA4, AA5, AB4, AB5, AC4, AC5, AD4, AD5, W1, Y1, Y2, Y3, AA1, AA2, AA3, AB1, AB2, AB3, AC1, AC2, ...
Page 91
... I/O- TS with pull up, slew Output, slew Output, slew Output Input w/ pulldown Input w/ pullup Input w/ pulldown Zarlink Semiconductor Inc. ZL50417 Description MII Management Data Clock – (Common for all MII Ports [15:0]) MII Management Data I/O – (Common for all MII Ports – [15:0]) Reference Input Clock Ports [15:0] – ...
Page 92
... ZL50417 Ball No(s) U29 M25_COL T29 M25_RXCLK W27, Y29, Y28, Y25, M25_RXD[9:0] AA29, AA28, AA27, AB29, AB28, AB27 T26 M25_TX_EN R26 M25_TX_ER T25 M25_ TXCLK P29 GREF_CLK0 K25, K26, M25, L26, M26_TXD[9:0] M26, L25, N26, N25, P26, P25 F28 M26_RX_DV G28 M26_RX_ER ...
Page 93
... Input w/ weak internal pull down resistors Input w/ weak internal pull down resistors I/O-TS Input with pull down Input with pull down Zarlink Semiconductor Inc. ZL50417 Description LED for Gigabit port 2 (full duplex + collision) LED for Gigabit port 2 System start operation Start initialization EEPROM read OK ...
Page 94
... ZL50417 Ball No(s) E1 SCLK K12, K13, K17,K18 VDD M10, N10, M20, N20, U10, V10, U20, V20, Y12, Y13, Y17, Y18 F13, F14, F15, F16, VCC F17, N6, P6, R6, T6, U6, N24, P24, R24, T24, U24, AD13, AD14, AD15, AD16, AD17 M12, M13, M14, M15, ...
Page 95
... Symbol I/O NA Default 1 Default 1 Default 1 Recommend disable (0) with pull-down Default 1 Default 1 Zarlink Semiconductor Inc. ZL50417 Description Reserved Pins. Leave unconnected. GIGA Link polarity 0 – active low 1 – active high RMII MAC Power Saving Enable 0 – No power saving 1 – power saving Giga Half Duplex Support ...
Page 96
... ZL50417 Ball No(s) A27 TSTOUT7 B27 TSTOUT8 C27 TSTOUT9 D27 TSTOUT10 C26 TSTOUT11 D26 TSTOUT12 D25 TSTOUT13 D24 TSTOUT14 E24 TSTOUT15 T26, R26 G0_TXEN, G0_TXER F26, E26 G1_TXEN, G1_TXER 96 Symbol I/O Default 1 Default 1 Default 1 Default 1 Default 1 Default 1 Default 1 Default: PCS Default: PCS Zarlink Semiconductor Inc. ...
Page 97
... Input signal with Schmitt-Trigger Output signal (Tri-State driver) Output signal with Open-Drain driver Input & Output signal with Tri-State driver Input & Output signal with Open-Drain driver Zarlink Semiconductor Inc. ZL50417 Description 0 – GPSI 1 - RMII Reserved - Must be pulled- down Programmable delay for internal OE_CLK from SCLK input ...
Page 98
... ZL50417 14.3 Ball Signal Name Ball No. Signal Name D20 LA_D[63] B21 LA_D[62] D19 LA_D[61] E19 LA_D[60] D18 LA_D[59] E18 LA_D[58] D17 LA_D[57] E17 LA_D[56] D16 LA_D[55] E16 LA_D[54] D15 LA_D[53] E15 LA_D[52] D14 LA_D[51] E14 LA_D[50] D13 LA_D[49] E13 LA_D[48] D21 LA_D[47] ...
Page 99
... AE19 NC AF23 AF21 M[15]_RXD[1] AG21 AJ19 M[14]_RXD[1] AH21 AF18 M[13]_RXD[1] AF19 AJ17 M[12]_RXD[1] AF17 AJ15 M[11]_RXD[1] AG17 Zarlink Semiconductor Inc. ZL50417 Signal Name LB_D[35] LB_D[34] LB_D[33] LB_D[32] LB_D[31] LB_D[30] LB_D[29] LB_D[28] LB_D[27] LB_D[26] LB_D[25] LB_D[24] LB_D[23] LB_D[22] M[4]_RXD[0] M[3]_RXD[0] M[2]_RXD[0] M[1]_RXD[0] ...
Page 100
... ZL50417 Ball No. Signal Name AC2 LB_D[4] AC3 LB_D[3] AD1 LB_D[2] AD2 LB_D[1] AD3 LB_D[0] N3 LB_A[20] N2 LB_A[19] N1 LB_A[18] P3 LB_A[17] P2 LB_A[16] P1 LB_A[15] R5 LB_A[14] R4 LB_A[13] R3 LB_A[12] R2 LB_A[11] R1 LB_A[10] T5 LB_A[9] T4 LB_A[8] T3 LB_A[7] T2 LB_A[6] T1 LB_A[5] W3 LB_A[4] W2 LB_A[3] V1 LB_ADSC# G1 LB_CLK V3 LB_WE# P4 LB_WE0# P5 LB_WE1# V2 LB_OE# U1 LB_OE0# AE8 M[5]_TXEN 100 Ball No ...
Page 101
... V27 RESERVED M26 W29 RESERVED L25 W28 RESERVED N26 W27 M25_RXD[9] N25 Y29 M25_RXD[8] P26 Y28 M25_RXD[7] P25 Zarlink Semiconductor Inc. ZL50417 Signal Name RESERVED RESERVED RESERVED RESERVED RESERVED M26_RXD[9] M26_RXD[8] M26_RXD[7] M26_RXD[6] M26_RXD[5] M26_RXD[4] M26_RXD[3] M26_RXD[2] M26_RXD[1] M26_RXD[0] RESERVED RESERVED ...
Page 102
... ZL50417 Ball No. Signal Name AH26 NC AF25 NC AH24 NC AG22 NC AH22 NC AE17 NC AG19 M[15]_TXD[0] AH18 M[14]_TXD[0] AF16 M[13]_TXD[0] AH16 M[12]_TXD[0] AH14 M[11]_TXD[0] AF13 M[10]_TXD[0] AH12 M[9]_TXD[0] AF10 M[8]_TXD[0] AH10 M[7]_TXD[0] B27 G2_LINK#/TSTOUT[8] A27 G2_DPCOL#/TSTOUT[7] E28 G2_RXTX#/TSTOUT[6] D28 G1_LINK#/TSTOUT[5] C28 ...
Page 103
... U17 VSS F14 M12 VSS F15 M13 VSS M14 VSS M15 VSS P17 VSS P18 VSS R12 VSS Zarlink Semiconductor Inc. ZL50417 Signal Name VDD VDD VSS VSS VSS VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC ...
Page 104
... ZL50417 14.4 AC/DC Timing 14.4.1 Absolute Maximum Ratings Storage Temperature-65C to +150C o Operating Temperature- Supply Voltage VCC with Respect to V Supply Voltage VDD with Respect to V Voltage on Input Pins-0 (VCC + 3.3 V) Caution: Stress above those listed may damage the device. Exposure to the Absolute Maximum Ratings for extended periods may affect device reliability ...
Page 105
... Figure 17 - Local Memory Interface – Input setup and hold timing Figure 18 - Local Memory Interface - Output valid delay timing LA_CLK L1 L2 LA_D[63:0] LA_CLK L3-max L3-min LA_D[63:0] L4-max L4-min LA_A[20:3] L6-max L6-min LA_ADSC# L7-max L7-min LA_WE[1:0]# #### L8-max L8-min LA_OE[1:0]# L9-max L9-min LA_WE# L10-max L10-min LA_OE# Zarlink Semiconductor Inc. ZL50417 105 ...
Page 106
... ZL50417 AC Characteristics – Local frame buffer SBRAM Memory Interface Symbol L1 LA_D[63:0] input set-up time L2 LA_D[63:0] input hold time L3 LA_D[63:0] output valid delay L4 LA_A[20:3] output valid delay L6 LA_ADSC# output valid delay L7 LA_WE[1:0]#output valid delay L8 LA_OE[1:0]# output valid delay L9 LA_WE# output valid delay ...
Page 107
... LB_A[21:2] L6-max L6-min LB_ADSC# L8-max L8-min LB_WE[1:0]# L9-max L9-min LB_OE[1:0]# L10-max L10-min LB_WE# L11-max L11-min LB_OE# Parameter Min (ns) 4 1.5 1 Zarlink Semiconductor Inc. ZL50417 -100MHz Max (ns) Note 25pf 30pf 30pf 25pf 25pf 25pf L ...
Page 108
... ZL50417 14.7 AC Characteristics 14.7.1 Reduced Media Independent Interface M[23:0] _TXD[1:0] 15 Figure Characteristics – Reduced media independent Interface M[23:0]_CRS_DV 15 Figure Characteristics – Reduced Media Independent Interface AC Characteristics – Reduced Media Independent Interface Symbol M2 M[15:0]_RXD[1:0] Input Setup Time M3 M[15:0]_RXD[1:0] Input Hold Time M4 M[15:0]_CRS_DV Input Setup Time ...
Page 109
... Data Sheet 14.7.2 Gigabit Media Independent Interface M25_RXD[15:0] M25_RX_CRS Figure Characteristics – Gigabit Media Independent Interface M25_TXCLK G12-max G12-min [7:0] M25_TXD [15:0] G13-max G13-min M25_TX_EN] G14-max G14-min M25_TX_ER Figure Characteristics- GMII M25_RXCLK G1 G2 [7: M25_RX_DV G5 G6 M25_RX_ER G7 G8 Zarlink Semiconductor Inc. ZL50417 109 ...
Page 110
... ZL50417 AC Characteristics – Gigabit Media Independent Interface Symbol G1 M[25]_RXD[7:0] Input Setup Times G2 M[25]_RXD[7:0] Input Hold Times G3 M[25]_RX_DV Input Setup Times G4 M[25]_RX_DV Input Hold Times G5 M[25]_RX_ER Input Setup Times G6 M[25]_RX_ER Input Hold Times G7 M[25]_CRS Input Setup Times G8 M[25]_CRS Input Hold Times G12 ...
Page 111
... M[26]_RXD[7:0] Input Hold Times Parameter Min (ns Table 13 - Input Setup Timing M26_TXCLK G12-max G12-min [7:0] G13-max G13-min M26_TX_EN] G14-max G14-min M26_TX_ER Figure Characteristics- GMII M26_RXCLK G1 M26_RXD[15:0] [7:0] G3 M26_RX_DV G5 M26_RX_ER G7 M26_RX_CRS Parameter 2 1 Zarlink Semiconductor Inc. Max (ns) Note -125Mhz Min (ns) Max (ns) ZL50417 Note: 111 ...
Page 112
... ZL50417 AC Characteristics – Gigabit Media Independent Interface G3 M[26]_RX_DV Input Setup Times G4 M[26]_RX_DV Input Hold Times G5 M[26]_RX_ER Input Setup Times G6 M[26]_RX_ER Input Hold Times G7 M[26]_CRS Input Setup Times G8 M[26]_CRS Input Hold Times G12 M[26]_TXD[7:0] Output Delay Times G13 M[26]_TX_EN Output Delay Times ...
Page 113
... Table 15 - Input Setup Timing LED_CLK LE5-max LE5-min LED_SYN LE6-max LE6-min LED_BIT Figure Characteristics – LED Interface Parameter Min (ns Table 17- AC Characteristics – LED Interface Zarlink Semiconductor Inc. Max (ns) Note: Variable FREQ. Note: Max (ns 30pf 30pf L ZL50417 113 ...
Page 114
... ZL50417 14.7.4 SCANLINK SCANCOL Output Delay Timing SCANLINK Figure 32 - SCANLINK SCANCOL Output Delay Timing Symbol C1 SCANLINK input set-up time C2 SCANLINK input hold time C3 SCANCOL input setup time C4 SCANCOL input hold time C5 SCANLINK output valid delay C7 SCANCOL output valid delay 114 SCANCLK C5-max ...
Page 115
... MDIO input hold time D3 MDIO output delay time MDC D1 D2 MDIO Figure 34 - MDIO Input Setup and Hold Timing MDC D3-max D3-min MDIO Figure 35 - MDIO Output Delay Timing Parameter Table 17 - MDIO Timing Zarlink Semiconductor Inc. 1MHz Note: Min (ns) Max (ns 50pf L ZL50417 115 ...
Page 116
... ZL50417 14.7.6 I²C Input Setup Timing Symbol S1 SDA input setup time S2 SDA input hold time S3* SDA output delay time * Open Drain Output. Low to High transistor is controlled by external pullup resistor. 116 SCL S1 SDA Figure 36 - I²C Input Setup Timing SCL S3-max S3-min SDA Figure 37 - I² ...
Page 117
... D2 D0 hold time D3 AutoFd output delay time D4 Strobe low time D5 Strobe high time Figure 38 - Serial Interface Setup Timing D3-max D3-min Parameter Min (ns Table 19 - Serial Interface Timing Zarlink Semiconductor Inc. ZL50417 Max (ns) Note 100pf L 117 ...
Page 118
NOTE: 1. CONTROLLING DIMENSIONS ARE DIMENSION "b" IS MEASURED AT THE MAXIMUM SOLDER BALL DIAMETER 3. SEATING PLANE IS DEFINED BY THE SPHERICAL CROWNS OF THE SOLDER BALLS THE NUMBER OF ...
Page 119
For more information about all Zarlink products Information relating to products and services furnished herein by Zarlink Semiconductor Inc. trading as Zarlink Semiconductor or its subsidiaries (collectively “Zarlink”) is believed to be reliable. However, Zarlink assumes no liability for errors ...