zl50232 Zarlink Semiconductor, zl50232 Datasheet - Page 30

• Manufacturer Part Number: zl50232
• Description: 32 Channel Voice Echo Canceller
• Manufacturer: Zarlink Semiconductor

Note: In order to correctly write to Control Register 1 and 2 of ECB, it is necessary to write the data twice to the register, one
immediately after another. The two writes must be separated by at least 350ns and no more than 20 us.
HPFDis
NLPDis
AutoTD
MuteR
PHDis
NBDis
MuteS
Bit 7
TDis
TDis
Power-up
00
hex
When high, tone detection is disabled. When low, tone detection is enabled. When both
Echo Cancellers A and B TDis bits are high, Tone Disable processors are disabled
entirely and are put into Power Down mode.
When high, the tone detectors will trigger upon the presence of a 2100 Hz tone regardless
of the presence/absence of periodic phase reversals. When low, the tone detectors will
trigger only upon the presence of a 2100 Hz tone with periodic phase reversals.
When high, the non-linear processor is disabled. When low, the non-linear processors
function normally. Useful for G.165 conformance testing.
When high, the echo canceller puts itself in Bypass mode when the tone detectors detect
the presence of 2100 Hz tone. See PHDis for qualification of 2100 Hz tones.
When low, the echo canceller algorithm will remain operational regardless of the state of
the 2100 Hz tone detectors.
When high, the narrow-band detector is disabled. When low, the narrow-band detector is
enabled.
When high, the offset nulling high pass filters are bypassed in the Rin and Sin paths.
When low, the offset nulling filters are active and will remove DC offsets on PCM input
signals.
When high, data on Sout is muted to quiet code. When low, Sout carries active code.
When high, data on Rout is muted to quiet code. When low, Rout carries active code.
PHDis
Bit 6
NLPDis
Bit 5
Functional Description of Register Bits
ECA: Control Register 2
ECB: Control Register 2
Zarlink Semiconductor Inc.
AutoTD
Bit 4
ZL50232
30
NBDis
Bit 3
HPFDis
Bit 2
01
21
MuteS
hex
hex
Bit 1
R/W Address:
R/W Address:
+ Base Address
+ Base Address
MuteR
Data Sheet
Bit 0