zl50211 Zarlink Semiconductor, zl50211 Datasheet - Page 21

• Manufacturer Part Number: zl50211
• Description: 256 Channel Voice Echo Canceller
• Manufacturer: Zarlink Semiconductor

7.5
To ensure fast initial convergence on a new call, it is important to clear the Adaptive Filter. This is done by putting
the echo canceller in bypass mode for at least one frame (125 µs) and then enabling adaptation.
Since the Narrow Band Detector is “ON” regardless of the functional state of the Echo Canceller it is recommended
that the Echo Cancellers are reset before any call progress tones are applied.
7.6
The EVP provides an interrupt pin (IRQ) to indicate to the HOST processor when a G.164 or G.165 Tone Disable is
detected and released.
Although each EVP may be configured to react automatically to tone disable status on any input PCM voice
channels, the user may want for the external HOST processor to respond to Tone Disable information in an
appropriate application-specific manner.
Each echo canceller will generate an interrupt when a Tone Disable occurs and will generate another interrupt
when a Tone Disable releases.
Upon receiving an IRQ, the HOST CPU should read the Interrupt FIFO Register. This register is a FIFO memory
containing the channel number of the echo canceller that has generated the interrupt.
All pending interrupts from any of the echo cancellers and their associated input channel number are stored in this
FIFO memory. The IRQ always returns high after a read access to the Interrupt FIFO Register. The IRQ pin will
toggle low for each pending interrupt.
After the HOST CPU has received the channel number of the interrupt source, the corresponding per channel
Status Register can be read from internal memory to determine the cause of the interrupt (see Table 3 for address
mapping of Status register). The TD bit indicates the presence of a Tone Disable.
The MIRQ bit 5 in the Main Control Register 0 masks interrupts from the EVP. To provide more flexibility, the MTDBI
(bit-4) and MTDAI (bit-3) bits in the Main Control Register<15:0> allow Tone Disable to be masked or unmasked
from generating an interrupt on a per channel basis. Refer to the Registers Description section.
8.0
The EVP JTAG interface conforms to the Boundary-Scan standard IEEE1149.1. This standard specifies a design-
for-testability technique called Boundary-Scan test (BST). The operation of the Boundary Scan circuitry is
controlled by an Test Access Port (TAP) controller. JTAG inputs are 3.3 Volts compliant only.
8.1
The TAP provides access to many test functions of the EVP. It consists of four input pins and one output pin. The
following pins are found on the TAP.
•
•
•
Test Clock Input (TCK)
The TCK provides the clock for the test logic. The TCK does not interfere with any on-chip clock and thus
remains independent. The TCK permits shifting of test data into or out of the Boundary-Scan register cells
concurrent with the operation of the device and without interfering with the on-chip logic.
Test Mode Select Input (TMS)
The logic signals received at the TMS input are interpreted by the TAP Controller to control the test
operations. The TMS signals are sampled at the rising edge of the TCK pulse. This pin is internally pulled to
V
Test Data Input (TDI)
Serial input data applied to this port is fed either into the instruction register or into a test data register,
depending on the sequence previously applied to the TMS input. Both registers are described in a
DD1
Call Initialization
Interrupts
Test Access Port (TAP)
JTAG Support
when it is not driven from an external source.
Zarlink Semiconductor Inc.
ZL50211
21
Data Sheet