am79c981 Advanced Micro Devices, am79c981 Datasheet - Page 20
am79c981
Manufacturer Part Number
am79c981
Description
Integrated Multiport Repeater Plus? Imr+? ??9
Manufacturer
Advanced Micro Devices
Datasheet
1.AM79C981.pdf
(40 pages)
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(Note 1)
(Note 2)
(Note 3)
Notes:
1. Externally generated signal illustrates internal IMR+ chip clock phase relationship.
2. CRS timing with the C-bit cleared (IMR+ Chip Programmable Options)
3. For Minimum Hub Mode
Port Activity Monitor
Two pins, CRS and STR, are used to serially output the
state of the internal Carrier Sense signals from the AUI
and the eight TP ports. This function together with exter-
nal hardware and/or software can be used to monitor re-
peater receive and/or collision activity.
1–90
CRS
TCK
STR
SO
X1
AMD
ASYNC
RESET
CRS
AUI
AUI
SO
CK
D
1/2 ’74
XTAL
OSC
Figure 3. Minimum Mode, Non-Intelligent Repeater Example
Q
CRS
Figure 4. Management Port Minimum Mode and
TP0
TP0
SO
Port Activity Monitor Signal Relationship
CRS
TP1
TP1
SO
TEST
X1
X2
RST
CRS
TP2
TP2
PRELIMINARY
SO
Am79C981
Am79C981
IMR+ Chip
SCLK
CK
D
1/2 ’74
CLR
CRS
TP3
TP3
SO
The following diagram shows typical external hardware
employed to convert the serial bit stream into parallel
form. The accuracy of the CRS signals is 10 Bit Times
(BT) (1 s). Specifically, a transition to active state by
any of the internal carrier sense bits that lasts for less
than 10BT is latched internally and is used to set the ap-
propriate bit during the next sample period.
SI
Q
Q
CRS
STR
TP4
TP4
SO
SO
TCK
TCK
CRS
TP5
TP5
SO
CK
SI
CK
T
P
7
CRS
TP6
TP6
SO
T
P
6
T
P
5
Register
SIPO
CRS
TP7
TP7
SO
17306B-7
T
P
0
U
A
I
17306B-8
CRS
AUI
AUI
SO