am79c972b Advanced Micro Devices, am79c972b Datasheet - Page 122

• Manufacturer Part Number: am79c972b
• Description: Pcnet?-fast+ Enhanced 10/100 Mbps Pci Ethernet Controller With Onnow Support
• Manufacturer: Advanced Micro Devices

2
1
0
122
GPSI
MII
LOOP
Table 21. Loopback Configuration
DTX
DRX
LOOP
0
1
1
0
0
1
INTL
0
1
0
0
0
0
This bit was called DTCR in the
LANCE (Am7990) device.
Read/Write accessible only when
either the STOP or the SPND bit
is set.
Read/Write accessible only when
either the STOP or the SPND bit
is set.
Loopback Enable allows the
Am79C972 controller to operate
in full-duplex mode for test pur-
poses. The setting of the full-
duplex control bits in BCR9 have
no effect when the device oper-
ates in loopback mode. When
LOOP = 1, loopback is enabled.
In combination with INTL and
MIIILP, various loopback modes
are defined as follows in Table
21.
Disable
Am79C972 controller not access-
ing the Transmit Descriptor Ring
and, therefore, no transmissions
are attempted. DTX = 0, will set
TXON bit (CSR0 bit 4) if STRT
(CSR0 bit 1) is asserted.
Disable Receiver results in the
Am79C972 controller not access-
ing the Receive Descriptor Ring
and, therefore, all receive frame
data are ignored. DRX = 0, will
set RXON bit (CSR0 bit 5) if
STRT (CSR0 bit 1) is asserted.
Refer to Loop Back Operation
section for more details.
Read/Wr ite acc es sible only
when either the STOP or the
SPND bit is set. LOOP is cleared
by H_RESET or S_RESET and
is unaffected by STOP.
MIIILP
0
0
0
0
1
0
Transmit
Normal Operation
Internal Loop
External Loop
Normal Operation
Internal Loop
External Loop
Function
results
Am79C972
in
CSR16: Initialization Block Address Lower
Bit
31-16 RES
15-0
CSR17: Initialization Block Address Upper
Bit
31-16 RES
15-0
CSR18: Current Receive Buffer Address Lower
Bit
31-16 RES
15-0
CSR19: Current Receive Buffer Address Upper
Bit
31-16 RES
15-0
Name
IADRL
Name
IADRH
Name
CRBAL
Name
CRBAU
Read/Write accessible only when
either the STOP or the SPND bit
is set.
zeros and read as undefined.
Read/Write accessible only when
either the STOP or the SPND bit
is set.
zeros and read as undefined.
Read/Write accessible only when
either the STOP or the SPND bit
is set.
zeros and read as undefined.
current receive buffer address at
which the Am79C972 controller
will store incoming frame data.
Read/Write accessible only when
either the STOP or the SPND bit
is set. These bits are unaffected
by H_RESET, S_RESET, or
STOP.
zeros and read as undefined.
current receive buffer address at
which the Am79C972 controller
will store incoming frame data.
Description
Reserved locations. Written as
This register is an alias of CSR1.
Description
Reserved locations. Written as
This register is an alias of CSR2.
Description
Reserved locations. Written as
Contains the lower 16 bits of the
Description
Reserved locations. Written as
Contains the upper 16 bits of the