am79c875 Advanced Micro Devices, am79c875 Datasheet
am79c875
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am79c875 Summary of contents
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... Am79C875 NetPHY™ 4LP Low Power Quad 10/100-TX/FX Ethernet Transceiver DISTINCTIVE CHARACTERISTICS I Four 10/100BASE-TX Ethernet PHY transceivers I Supports RMII (Reduced MII) interface I 125 meter (m) MLT-3 and Baseline Wander operation I Low power consumption — 1.3 Watt (W) typical (1:1 magnetics) — 1.2 W typical (1.25:1 magnetics) I Power management modes: — ...
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... PCS PMA Clock Recovery Framer Link Monitor 4B/5B Signal Detect Stream Cipher 25 MHz 10TX 10BASE-T 10RX Control/Status 20 MHz PLL Clk Generator Test LED Control REFCLK TEST LED [3:0] Drivers Am79C875 100TX TP_PMD MLT-3 TX+ BLW 100RX TX- Mux Transformer RX+ RX- RX FLP Auto- 25 MHz Negotiation 22236G-1 ...
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... CONNECTION DIAGRAM Am79C875 22236G-2 3 ...
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... LOGIC SYMBOL 4 Am79C875 ...
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... NetPHY™ 4LP Low Power Quad 10/100-TX/FX Ethernet Transceiver Valid Combinations list configurations planned to be sup- KC ported in volume for this device. Consult the local AMD sales office to confirm availability of specific valid combinations and KI to check on newly released combinations. Am79C875 Valid Combinations 5 ...
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... Am97C973B/975B PCnet-FAST™ III Single-Chip 10/100 Mbps PCI Ethernet Controller with Integrated PHY Am79C976 PCnet-PRO™ 10/100 Mbps PCI Ethernet Controller Am79C978A PCnet-Home™ Single-Chip 1/10 Mbps PCI Home Networking Controller Physical Layer Devices (Single-Port) Am79C874 NetPHY™ 1LP Low Power 10/100-TX/FX Ethernet Transceiver Am79C901A HomePHY™ Single-Chip 1/10 Mbps Home Networking PHY 6 Am79C875 ...
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... MLT-3 Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .39 MII Management Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .40 Independent RMII Mode Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .41 PHYSICAL DIMENSIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .45 PQR100 (measured in millimeters .45 ERRATA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .46 Revision B.4 Errata Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .46 Errata for NetPHY™ 4LP B. .46 REVISION SUMMARY .48 Revision .48 Revision .48 Revision .48 Revision .48 Revision .48 Am79C875 7 ...
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... Table 16. Miscellaneous Features Register (Register 16 .31 Table 17. Interrupt Control/Status Register (Register 17 .31 Table 18. Diagnostic Register (Register 18 .32 Table 19. Test Register (Register 19 .32 Table 20. Miscellaneous Features 2 Register (Register 20 .32 Table 21. Receive Error Counter (Register 21 .33 Table 22. Mode Control Register (Register 24 .33 8 Am79C875 ...
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... REFCLK LEDACT_LINK[2] 67 CVDD LEDSPD[2]/ 68 RXD[1]_[1] FORCE100 OVDD 69 RXD[1]_[0] RXD[3]_[1] 70 RX_ER[1] RXD[3]_[0] 71 CRS_DV[1] RX_ER[3]/ 72 OGND PHYAD_ST CRS_DV[3] 73 CGND CGND 74 TXD[1]_[1] TXD[3]_[1] 75 TXD[1]_[0] Am79C875 Pin No. Pin Name 76 TX_EN[1] 77 CVDD 78 RXD[0]_[1] 79 RXD[0]_[0] 80 OVDD 81 RX_ER[0] 82 CRS_DV[0]/ 83 CGND 84 TXD[0]_[1] 85 TXD[0]_[0] 86 TX_EN[0] 87 OGND LEDDPX[1]/ 88 PHYAD[4] LEDACT_LINK[1]/ 89 PHYAD[3] ...
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... PHYAD of each port is 00001, 00010, 00011, and 00100, respectively. This allows a method of avoiding setting an address to 00000, which could cause problems with some MACs. CRS_DV[3:0] Carrier Sense/Data Valid The CRS_DV pin is asserted high when media is non-idle. Am79C875 Analog Output Input Input Input Output Output Input/Output ...
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... FORCE100: Force 100BASE-X Operation. When this signal is pulled high and ANEGA is low at reset, all ports will be forced to 100BASE-TX operation. When asserted low and ANEGA is low, all ports are forced to Am79C875 Input/Output, Pull-Up Input/Output, Pull-Up Input/Output, Pull-Up ...
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... Ground These pins are the ground for analog circuit. GAVDD Power These pins are the +3.3 V power supply for common analog circuits. GAGND Ground Analog This pin is the ground for common analog circuits. Am79C875 Digital Digital Digital Digital Analog Analog Analog Analog ...
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... The data on RXD[1:0] is considered valid once CRS_DV is asserted. However, since the assertion of CRS_DV is asynchronous relative to REF_CLK, the data on RXD[1:0] is “00” until proper receive signal decoding takes place. Note: CRS_DV is asserted asynchronously in order to minimize latency of control signals through the PHY. Am79C875 RXD[X]_[1:0] CRS_DV[X] RX_ER[X] TXD[X]_[1:0] TX_EN[X] 13 ...
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... At a REF_CLK frequency of 50 MHz, the value on RXD[1:0] is valid such that RXD[1:0] may be sampled every tenth cycle, regardless of the starting cycle within the group and yield the correct frame data. Am79C875 ...
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... RMII inter- face. For 100BASE-FX operation, the NetPHY™ 4LP re- ceives a PECL data stream from the fiber optic trans- ceiver and decodes that data stream. 100BASE-FX operation is possible only on Port 3. Am79C875 ...
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... Otherwise, when a valid signal is detected for a minimum period of time, the link monitor will then enter link pass state which transmit and receive functions will be entered. Am79C875 ...
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... MAUs, and trans- ceiver functions. The NetPHY™ 4LP transceiver receives 10-Mbps data from the MAC, switch, or re- peater across the RMII at 5 million di-bits per second. It then Manchester encodes the data before transmis- sion to the network. Am79C875 Interpretation Data 0 Data 1 Data 2 Data 3 ...
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... Thus, the proper signal will appear on the MDI regardless of the polarity of the input signals. The internal polarity detection and correction circuitry is set during the reception of the normal link pulses (NLP) or packets. The receiver detects the polarity of the input Am79C875 ...
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... The equalizer tunes itself automatically to the any cable length to compen- sate for the amplitude and phase distortion incurred from the cable. Baseline Wander Compensation The 100BASE-TX data stream is not always DC bal- anced. The media, with transformer and common Am79C875 22236G-8 19 ...
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... The data is presented to PCS at re- ceive data register output, gated by the 25-MHz RX_CLK Isolation Transformer with common-mode chokes * 1:1 or 1.25:1 * 0.1 µF 75 Ω 1:1 * (Note 4) 0.1 µF 75 Ω 470 pF (chassis ground) Am79C875 RJ45 Connector (8) (7) TX+ (1) (5) (4) TX– (2) Ω 75 Ω RX+ (3) RX– (6) 470 pF (chassis ground) 22236G-9 ...
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... Up to 25% of repeater and switch ports are unconnected to allow room for fu- ture expansion. With NetPHY™ 4LP, unconnected ports have their receiver disabled until energy is de- tected. The power savings is most notable on uncon- Am79C875 2 = 1.56). Thus, the 21 ...
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... LED Display Configuration LEDACT_LINK[N] LEDSPD[N] LED On LED On LED On LED On LED On LEDXXX/XXX 1 - 4.7 kΩ Configure HIGH with an Active-LOW LED Figure 8. LED Port Configuration Am79C875 ) should be selected L LEDDPX[N] LED Off LED Off LED On LED Off LED On LED On LED Off LED Off LED Off LED On ...
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... The address shifting carries over the entire address space. If PHYAD[4:2] is set to 111, the PHYAD for each port is as follows: Port 0 Port 1 Port 2 Port 3 PHYAD REGADD TA 00000 RRRRR Z0 00000 RRRRR 10 Am79C875 TA DATA IDLE Z0 D........... D...........D Z 00001 00010 00011 00100 11101 11110 ...
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... Register Address TA MII Control, 0h Write Operation Table 5. NetPHY™ 4LP MII Management Register Address (in decimal 8- 25-31 Am79C875 Register Data Idle ...
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... PHY channels. All registers are available on a per port basis. Table 6. Legend for Register Tables Type Description RW Readable and writable SC Self Clearing LL Latch low until clear RO Read Only RC Cleared on the read operation LH Latch high until clear Am79C875 25 ...
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... Enable collision test, which issues the COL signal in response to the assertion of TX_EN signal. Collision test Collision Test enabled regardless of the duplex mode disable COL test. 0 6:0 Reserved Write as 0, ignore on read. 26 MII Management Control Register (Register 0) Am79C875 Read/ Write Default RW/ Set by RW FORCE100 pin Set by ...
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... Link is established, however, if the NetPHY™ 4LP device link fails, this bit will be cleared and remain cleared until register is read via management interface Link is down Jabber condition detect Jabber condition detected Extended register capable. This bit is tied permanently to one. Am79C875 Read/ Write Default RO 0 Set by RO ...
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... No 100BASE-TX half duplex capability. Default is set by Register 1.13 Mbps with full duplex 10Mbps full duplex capability. Default is set by Register 1.12 Mbps with half duplex Mbps half duplex capability Default is set by Register 1.11. [00001] = IEEE 802.3 Am79C875 Read/ Write Default RO 0022(H) Read/ Write Default ...
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... No Link Partner Acknowledgement Link Partner message Page Request Link partner Message Page Request Link Partner can Comply with Next Page Request Link Partner cannot Comply with Next Page Request. Link Partner Toggle. Link Partner’s Message Code. Am79C875 Read/ Write Default ...
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... Message page 0 = Un-formatted page. Acknowledge Will comply with message Cannot comply with message. Toggle Previous value of transmitted link code word equals Previous value of transmitted link code word equals to 1 Message/Un-formatted Code Field. Am79C875 Read/ Write Default RO 0 RO/ ...
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... This bit is set when link status switches from OK status to Non- Link_Not_OK Int status (Fail or Ready R_Fault_Int This bit is set when remote fault is detected A_Neg_Comp Int This bit is set when Auto-Negotiation is complete. Interrupt Control/Status Register (Register 17) Am79C875 Read/ Write Default 00000 RO 0 ...
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... The value is read back from the equalizer, and the measured value is not absolute. 20 3:0 Reserved Ignore when read. 32 Diagnostic Register (Register 18) Table 19. Test Register (Register 19) Miscellaneous Features 2 Register (Register 20) Am79C875 Read/ Write Default RO/RC 0 ...
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... The default of this bit is set by power on read value of FX_DIS Reserved Write as 0, ignore when read. Set this bit to logic 1 to select 100BASE-FX mode, set to logic FX_SEL select 100BASE-TX. Am79C875 Read/ Write Default RW 0000 (hex) Read/ Write Default RW 0 ...
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... PECL Load V DD PECL Load V DD MLT-3/10BASE-T Test Load MLT-3/10BASE-T Test Load V = Maximum 0 MLT-3/10BASE-T Test Load MLT-3/10BASE-T Test Load MLT-3/10BASE-T Test Load Am79C875 ) . . . . . . . . . . . . . . +3.3 V ± +3.3 V ±5% DD Maximum Units 0.8 V 2.0 V 0.4 V 2.4 V 0.4 V – 0 – 1.5 V – ...
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... MLT-3/10BASE-T Test Load 0.4 V < V < V OUT DD Test Conditions Minimum V = maximum - DD (Note 13 maximum - DD MAX. Tested within limits of V SDA MIN. Tested within limits of V SDD Am79C875 Minimum Maximum 300 585 150 293 -60 60 2.2 2.8 -30 100 Typical Maximum Units 260 480 mA (Note 11,12) ...
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... Must be Steady May Change from May Change from Don’t Care, Any Change Permitted Does Not Apply Figure 10. MLT-3 Receive Input Am79C875 OUTPUTS Will be Steady Will be Changing from Will be Changing from Changing, State Unknown Center Line is High- Impedance “ ...
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... TX+ TX- 0.01 µF Figure 12. MLT-3 and 10BASE-T Test Load with 1.25:1 Transformer Ratio V TXOS +V TXOUT TX± -V TXOUT Figure 13. Near-End 100BASE-TX Waveform Am79C875 Isolation Transformer • 1:1 • 100 Ω Ω 5% 0.01 µF Chassis Ground Isolation Transformer • 1:25:1 • 100 Ω Ω 5% 0.01 µF ...
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... V TX10NE TX± 10BASE-T 0 Figure 14. Near-End 10BASE-T Waveform Pin 5 V Test Load Figure 15. Recommended PECL Test Loads 82.5 Ω Pin 130 Ω 3.3 V Test Load Am79C875 22236G- 3 Ω 183 Ω 22236G-17 ...
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... Duty Cycle Distortion Peak to Peak TXDCD t Transmit Jitter Using Scrambled Idle Signals TXJ TX± t CLK CLKL CLKH CLF Figure 16. Clock Signal TXR TXF XTDCD Figure 17. MLT-3 Test Waveform Am79C875 Min. Max. 19.999 20.001 CLR 80% 20% Min. Max. 3.0 5.0 3 ...
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... MDIO Hold Time From Rising Edge of MDC MDH MDC MDIO Figure 18. Management Bus Transmit Timing MDC MDIO Figure 19. Management Bus Receive Timing 40 t MDPER t t MDWH MDWL t MDPD mdio_tx.vsd t t MDS MDH Am79C875 Min. Max. Unit 22236G-20 22236G-21 ...
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... Required De-assertion Time Between Packets TIDLE100 REFCLK t RS100 TX_EN[X] TXD[X]_[1:0] TX± Figure 20. RMII 100 Mbps Transmit Start of Packet REFCLK TX_EN[X] TX± Figure 21. RMII 100 Mbps Transmit End of Packet Timing t RS100 t RTJ100 t TIDLE100 /T/ Am79C875 Min. Max. Unit 100 ns 120 - ns t RH100 /J/ 22236G-22 ...
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... RX± CRS_DV[X] REFCLK RXD[X]_[1:0] Figure 22. 100 Mbps RMII Receive Start of Packet Timing RX± CRS_DV[X] REFCLK RXD[X]_[1:0] Figure 23. 100 Mbps RMII Receive End of Packet Timing 42 /J/ t RJC100 /T/R/ t RTC100 t RCR100 Am79C875 Min. Max. 80 150 5 13 120 190 t RCR100 22236G-24 t RCR100 22236G-25 Unit ...
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... Required De-assertion Time Between Packets TIDLE10 REFCLK TX_EN[X] TXD[X]_[1:0] TX± Figure 24. RMII 10 Mbps Transmit Start of Packet REFCLK t RS10 TX_EN[X] TX± Figure 25. RMII 10 Mbps Transmit End of Packet Timing t RS10 t RTP10 t TIDLE10 Am79C875 Min. Max. Unit 240 360 ns 300 - RS10 ...
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... REFCLK RXD[X]_[1:0] Figure 26. 10 Mbps RMII Receive Start of Packet Timing RX± CRS_DV[X] REFCLK RXD[X]_[1:0] Figure 27. 10 Mbps RMII Receive End of Packet Timing 44 t RSPC10 t REPC10 t RCR10 t RCR10 Am79C875 Min. Max. Unit 200 350 130 190 ns t RCR10 22236G-28 22236G-29 ...
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... PHYSICAL DIMENSIONS* PQR100 (measured in millimeters) *For reference only. BSC is an ANSI standard for Basic Space Centering. Am79C875 45 ...
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... This is a minor issue. If the packet does not terminate properly, RX_ER is delayed 1-2 clock cycles. The issue is believed to be minor since the likelihood of encountering improperly termi- nated data packets is small. However, it will affect the recording of errors by the system. (UNH 1.24) WORKAROUND: There is no external workaround. STATUS: This errata will not be fixed. 46 Am79C875 ...
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... Very rarely do systems rely on Parallel Detect to set the speed of the link. Note that RMII operation is by definition, full-duplex. WORKAROUND: Full-duplex operation must be set through management pins, Register 0, bit 8. STATUS: This errata will not be fixed. Am79C875 47 ...
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... AMD, the AMD logo, and combinations thereof are trademarks of Advanced Micro Devices, Inc. NetPHY is a trademark of Advanced Micro Devices, Inc. Product names used in this publication are for identification purposes only and may be trademarks of their respective companies new and I maximum values Am79C875 ...