mh2040 Music Semiconductors, Inc., mh2040 Datasheet - Page 14

• Manufacturer Part Number: mh2040
• Description: Hla Packaged Asynchronous Data Recognition And Recall Processor
• Manufacturer: Music Semiconductors, Inc.

The Address Database
The Address Database is organized as 4096, 64-bit
locations: location 0000H as the highest-priority location,
and location 0FFFH as the lowest-priority location. Write
cycles to the next free address start at location 0000H
when the MH2040 is empty, and continue down to 0FFFH
or 1FFFH when it becomes full.
Each 64-bit location in the Address Database array has one
extra bit, the Validity bit, which is used to indicate whether
the location is empty or has valid contents. When the
Validity bit is HIGH, the location is empty and is not
compared during Comparison cycles; when it is LOW the
contents are valid and will be compared during a
Comparison cycle. The Validity bits are set or reset during
Write cycles through the /VB line. The Validity bit of a
location is accessed on the /VB line during a Read cycle.
The Validity bits can be set and reset through control
states. The Validity bits also are used in the generation of
the next free address value.
Address Database Access
Data is written to or read from the Address Database array
either randomly by address, or associatively by
comparison and next free address. Random addressing can
be either direct with the address on the DSC and AC11-0
lines (/AV=LOW) or indirect with the address held in the
Address register. Address Database access is controlled
through the control states on the DSC and AC11-0 lines
(/AV=HIGH) in Hardware Control mode, or through the
Instruction register in Software Control mode.
Chip Select
There are two methods of selecting an MH2040: through
Hardware control inputs /CS1 and /CS2, and through
software control through the Data Select register.
Chip Select Inputs
The Chip Select lines /CS1 and /CS2 enable an MH2040
to participate in a control cycle. If either /CS1 or /CS2 are
LOW the device is selected. By connecting all the /CS1
lines together in a multi-device system, and decoding the
lines to each individual device's /CS2 line, control states
can operate locally within a single device or globally in all
devices. Control states can be broadcast to all devices
within the system by pulling the /CS1 lines LOW, for
operations such as Write Comparand register; individual
devices can be selected to respond to a control state such
as Write at Address by pulling a single decoded /CS2 line
LOW.
HARRP - HLA Packaged Asynchronous Data Recognition-Recall Processors
14
Device Select Register
One dedicated line is needed per device to do local
selection of one device within a multi-device system. In
cases where control lines are at a premium, the Device
Select register can be used as the method of selection. If
Device Select Register bit DS8 is LOW, only the device or
devices whose Page Address value, held in Configuration
Register bits FR3:0, match with the Device Select Register
bits DS3-0 will be selected. Note that the match condition
of the Device Select register is ORed with the state of the
/CS1 and /CS2 lines. If DS8 is HIGH, the device remains
unselected through the Device Select register.
The conditions of the Device Select register, the /CS1 and
/CS2 lines are sampled at the time of the falling edge of /E.
In a particular MH2040 within a system, that CAM will be
selected under the following conditions:
Therefore, the /CS1 lines of all devices are tied together
for global cycles that broadcast control states to all devices
within the system; then, for local cycles, an individual
device is selected by loading all the Device Select
Registers bit DS8 LOW and bits DS3-0 with the Page
Address value of the device to be selected. On a
subsequent cycle, /CS1 and /CS2 remain HIGH, and only
the device whose Page Address value matches with its
DS3-0 will respond. After an individual device has been
selected, a global Write cycle to the Device Select register
using /CS1 line is executed to select another device, or to
disable the software chip select mechanism altogether.
Vertical Cascading
A system of any practical depth can be designed by
vertically cascading MH2040s. The scheme uses a daisy
chain to provide system level prioritization as well as
Match, Multiple Match, and Full flags. There are three
daisy chains: Match, Multiple Match, and Full.
When a control state is broadcast that accesses the
highest-priority matching location or Status register, the
daisy chain ensures that only the device that responds is
the one with the highest-priority match in the system. All
other devices will have their DQ31-0 lines and PA:AA bus
outputs held in high-impedance. Therefore, the Match
Flag daisy chain controls access to the system resources
for control states that are conditional on the results of the
previous Compare cycle.
During a Comparison cycle, the Match and Multiple
Match flags will not change until /E goes HIGH during
that cycle. At this time, the daisy chain starts to resolve
(/CS1=LOW) OR (/CS2=LOW)
OR ((DS8 = LOW) AND (DS3-0 = PA3-0))
Rev. 1.0