mh2040 Music Semiconductors, Inc., mh2040 Datasheet - Page 17

• Manufacturer Part Number: mh2040
• Description: Hla Packaged Asynchronous Data Recognition And Recall Processor
• Manufacturer: Music Semiconductors, Inc.

External Prioritization
For systems where the propagation delay associated with
the Match Flag daisy chain is unacceptable, the MH2040
supports
prioritization, each /MF output is fed to a 1 of N
prioritizing circuit whose outputs are fed back to the /CS
and /OE inputs of the respective MH2040s. Access to the
Highest-Priority Match Memory location or Status register
is accomplished by only enabling the /CS to the
Highest-Priority Match device based on the status of the
/MF flags in the system. Likewise, access to the
Highest-Priority Match device's PA:AA bus match address
result is accomplished by enabling only the /OE line to the
Highest-Priority Match device.
Initialization
After power is applied to the MH2040 the /RESET line
must be pulled LOW for at least 50 ns to ensure that the
device establishes its correct initial operating conditions.
There are control states to initialize the system-level
operating conditions that can be run once the device or
devices in the system have been reset after power has been
applied.
Reset
The Reset condition occurs when the /RESET line is
pulled LOW (Hardware reset,) or when the Reset Control
state is executed (Software reset.) The conditions after a
reset are shown in Table 2.
The Instruction register is enabled for Software Control
mode. To activate Hardware control, the appropriate value
should be written to the Configuration register in two
cycles from the DQ31-0 lines.
For a Hardware reset, FR25, which defines the lowest
priority device, is set HIGH. This means that either FR25
must be set LOW in the lowest-priority device, or a
Memory access cycle or a Compare cycle that generates a
match must be executed for there to be any response when
reading the PA:AA bus or the Status register.
Rev. 1.0
external
HARRP - HLA Packaged Asynchronous Data Recognition-Recall Processors
prioritization.
Using
external
17
System Initialization
Once the MH2040 devices in the system have been reset,
the system operating conditions must be set up. The
MH2040 is reset to Software Control mode, so a value
must be written to the Configuration register to set the
persistent operating state of the device. This first write to
the devices in the system must be through Software
control. The following sequence writes a new value to the
Configuration register under software control:
If the devices in a vertically cascaded system are to be
selected solely through the Device Select register, then the
Page addresses must be set to unique values in each
device. However, to set the Page address in each
Configuration register in turn would require that each
device already had a unique Page Address value. To
overcome this dilemma, there are two special control
states that allow the Page Address registers to be set
individually in this circumstance. Once the general
operating
broadcasting a configuration value to all the MH2040s in
the system, the Page Address values must be set to a
unique value in each device. This is done through a
sequence of WR PA control states, each executed with a
unique value on the DQ31-0 lines. This control state
writes the DS3-0 value into the Page Address field of the
Configuration register of the highest-priority empty
device, and then sets the Full flag of that device to indicate
full (LOW). The next WR PA will therefore be directed to
the next lower-priority device within the system. The
sequence continues until all Page Address values have
been written. The RST FF control state is then broadcast to
all devices to set the Full flags back to Empty, and the
system is then ready for normal operation.
1. Write 006H to MH2040s (/AV = HIGH, DQ13 =
LOW).
The value 006H is the control state Write to
Configuration register, WR FR, with no mask. /AV
being HIGH indicates that this is the instruction to be
written to the Instruction register, and DQ13 being
LOW indicates that it is a Write cycle.
2. XXXXXXXXH to MH2040s (/AV=LOW). The
value XXXXXXXXH is written to the Configuration
register, and if FR27-26=00 then the devices are set to
operate in Hardware Control mode.
AV being LOW causes the control state to execute
using the data present on the DQ31-0 lines.
conditions
have
been
established
by