ttsv02622 ETC-unknow, ttsv02622 Datasheet
ttsv02622
Related parts for ttsv02622
ttsv02622 Summary of contents
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... Low-power 3.3 V supply. –40 °C to +125 °C industrial temperature range. 272-pin ball grid array (PBGA) package. Description The TTSV02622 can support a 1.24 Gbits/s interface for backplane connections. The 1.24 Gbits/s inter- face is implemented as dual 622 Mbits/s LVDS links. The HSI macrocell is used for clock/data recovery (CDR) and MUX/deMUX between 77 ...
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... TTSV02622 STS-24 Backplane Transceiver Description (continued STS-24 IN DUAL STS-12 FORMAT DUAL STS-12 Figure 1. Byte Ordering on Input/Output Interface in STS-12 Mode ...
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... LVDS Receiver Buffer Capabilities ...................................................................................................................... 52 Clock and Data Recovery (CDR)............................................................................................................................ 54 Input Data ............................................................................................................................................................ 54 Jitter Tolerance .................................................................................................................................................... 54 Generated Output Jitter ....................................................................................................................................... 54 PLL....................................................................................................................................................................... 54 Input Reference Clock ......................................................................................................................................... 54 Timing Characteristics ............................................................................................................................................ 55 CPU Interface Timing........................................................................................................................................... 61 Outline Diagram...................................................................................................................................................... 63 272-Pin PBGA...................................................................................................................................................... 63 Ordering Information............................................................................................................................................... 64 Agere Systems Inc. TTSV02622 STS-24 Backplane Transceiver Table of Contents Page 3 ...
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... Figure 1. Byte Ordering on Input/Output Interface in STS-12 Mode ........................................................................ 2 Figure 2. Pin Diagram of 272-Pin PBGA (Bottom View)........................................................................................... 6 Figure 3. Suggested Schematic for 1.0 V and 1.4 V Reference Voltages.............................................................. 16 Figure 4. Alignment of Two STS-12 Streams ......................................................................................................... 17 Figure 5. Interior View of TTSV02622 .................................................................................................................... 18 Figure 6. Interconnect of Streams for FIFO Alignment........................................................................................... 19 Figure 7. Transmitter Block .................................................................................................................................... 22 Figure 8. Receiver Block ........................................................................................................................................ 24 Figure 9 ...
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... Table 22. Output Parallel Port Timing Requirements ............................................................................................. 57 Table 23. Protection Switch Timing Requirements................................................................................................. 58 Table 24. Input Serial Port Timing Requirements................................................................................................... 59 Table 25. Output Serial Port Timing Requirements................................................................................................ 60 Table 26. Write Transaction Timing Requirements ................................................................................................ 61 Table 27. Read Transaction Timing Requirements ................................................................................................ 62 Agere Systems Inc. TTSV02622 STS-24 Backplane Transceiver List of Tables Page 5 ...
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... TTSV02622 STS-24 Backplane Transceiver Pin Information Figure 2. Pin Diagram of 272-Pin PBGA (Bottom View June 2003 A1 BALL PAD CORNER Agere Systems Inc. ...
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... DOUTA4 B16 A17 DOUTA0 B17 A18 DOUTA_C1J1 B18 A19 DOUTB7 B19 A20 DOUTB6 B20 Note: NC refers to no connect. Do not connect pins so designated. Agere Systems Inc. TTSV02622 STS-24 Backplane Transceiver Signal Name Pin Signal Name TDO C1 TRSTN C2 TSTMD C3 LVDS_EN SCANEN DXN ...
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... TTSV02622 STS-24 Backplane Transceiver Pin Information (continued) Table 1. Pin Assignments for 272-Pin PBGA by Pin Number Order (continued) Pin Signal Name Pin E1 STS_INA_P H17 E2 STS_INA_N H18 E3 CTAP_REFA H19 E4 NC H20 E17 NC J1 E18 NC J2 E19 NC J3 E20 STS_INB_P J9 F2 STS_INB_N J10 ...
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... V16 U17 V V17 SS U18 DINB2 V18 U19 DINB1 V19 U20 DINB0 V20 Note: NC refers to no connect. Do not connect pins so designated. Agere Systems Inc. TTSV02622 STS-24 Backplane Transceiver Signal Name Pin Signal Name MRESET W1 EXDNUP ECSEL W2 TSTPHASE LOOPBKEN W3 TSTMUX8S TSTMUX6S W4 TSTMUX5S TSTMUX2S ...
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... TTSV02622 STS-24 Backplane Transceiver Pin Information (continued) Table 2. Pin Assignments for 272-Pin PBGA by Signal Name Signal Name Pin Signal Name BYPASS T2 CPU_ADDR0 Y8 CPU_ADDR1 W8 CPU_ADDR2 V8 CPU_ADDR3 Y7 CPU_ADDR4 W7 DOUTA_C1J1 CPU_ADDR5 V7 DOUTA_PAR CPU_ADDR6 U7 DOUTA_SPE CPU_DATA0 Y12 DOUTA0 CPU_DATA1 W12 DOUTA1 CPU_DATA2 V12 DOUTA2 CPU_DATA3 ...
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... NC W15 STS_INB_N NC W16 STS_INB_P NC W17 STS_OUTA_N NC W18 STS_OUTA_P NC W19 STS_OUTB_N — — Note: NC refers to no connect. Do not connect pins so designated. Agere Systems Inc. TTSV02622 STS-24 Backplane Transceiver Pin Signal Name NC W20 STS_OUTB_P NC Y1 SYS_CLK NC Y2 SYS_FP NC Y6 TCK NC Y10 TDI NC Y13 ...
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... TTSV02622 STS-24 Backplane Transceiver Pin Information (continued) Table 3. Pin Descriptions Pin Symbol N18, N19, N20, DINA[7:0] P17, P18, P19, P20, R19 R20 DINA_PAR R18, T17, T18, DINB[7:0] T19, T20, U18, U19, U20 V20 DINB_PAR A15, B15, C15, DOUTA[7:0] A16, B16, C16, ...
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... M18 SYS_FP M19 LINE_FP M17 SYS_CLK A7 PROT_SW_A B7 PROT_SW_C V10 INT_N W9 RST_N Agere Systems Inc. TTSV02622 STS-24 Backplane Transceiver Type I/O TTL O/ TOH serial link output for receiver #2. HI-Z/ Pull-up TTL O/ Rx TOH serial link clock enable. HI-Z/ Pull-up TTL O/ Rx TOH serial link frame pulse. ...
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... TTSV02622 STS-24 Backplane Transceiver Pin Information (continued) Table 3. Pin Descriptions (continued) Pin Symbol Y9 HIZ_N K1 PLL_REF M1 REF10 M2 REF14 M3 LVDS_RESH M4 LVDS_RESL A5 DXP B6 DXN K2 PLL_VDDA K3 PLL_VSSA A2 TCLK A3 TDI A4 TMS B1 TDO B2 TRSTN B3 TSTMD B4 SCANEN C3 LVDS_EN T1 TSTMODE T2 BYPASS U1 TSTCLK V1 MRESET T3 RESETRN T4 RESETTN U2 TSTSHFTLD 14 Type I/O TTL I/ Global 3-state control. ...
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... J12, K9, K10, K11, K12, L9, L10, L11, L12, M9, M10, M11, M12 D6, D11, D15, F4 F17, K4, L17, R4, R17, U6, U10, U15 Agere Systems Inc. TTSV02622 STS-24 Backplane Transceiver Type I/O — I/ Enables external test control of 622 MHz clock phase Pull-down selection. — I/ Direction of phase change. ...
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... TTSV02622 STS-24 Backplane Transceiver Pin Information (continued) REF10 REF14 Figure 3. Suggested Schematic for 1.0 V and 1.4 V Reference Voltages 16 3.3 V 3.3 V 2. June 2003 10 nF Agere Systems Inc. ...
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... The line side will receive/transmit frame-aligned streams of STS-12 data. All frames transmitted to the line will be aligned to the line frame pulse, which will be provided to the TTSV02622. All frames received from the line will be aligned to the system frame pulse, which will be supplied to the TTSV02622. ...
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... SOFT CTL POINTER MOVER STS-24 FIFO TOH CLK SOFT CTL CH#1 CH#2 RX TOH PROCESSOR CPU INTERFACE (ASYNC RST_N CS_N RD/WR_N (HARD RST) Figure 5. Interior View of TTSV02622 June 2003 DUAL CHANNEL TRANSMITTER 2 FRAME TX CH#1 LVDS PROC. (MACRO) OUT #1 2 FRAME TX CH#2 LVDS PROC. (MACRO) OUT #2 77.76 ...
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... LVDS buffers and TTL buffers for that channel. When all channels are powered down, PLL in the CDR mod- ule is also powered down. In addition, a pin has been added to enable the LVDS pins during boundary scan. This pin should be pulled high on the board for functional operation. Agere Systems Inc. TTSV02622 STS-24 Backplane Transceiver STS-12 STREAM A FIFO SYNC ...
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... TTSV02622 STS-24 Backplane Transceiver Supervisory Features Parallel bus integrity: — Parity error checking is implemented on each of the four parallel input buses. Even and odd parity is sup- ported as controlled from the CPU interface (per device control). Upon detection of an error, an interrupt is raised. This feature per-channel basis. ...
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... Scrambler/descrambler disable: — There is a scrambler/descrambler disable feature, allowing the user to disable the scrambler of the transmitter and the descrambler of the receiver. The B1 is calculated (in transmitter and receiver) on the nonscrambled data stream. This feature is per device. Agere Systems Inc. TTSV02622 STS-24 Backplane Transceiver 21 ...
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... TTSV02622 STS-24 Backplane Transceiver Transmit Direction (Line to Backplane) Each TOH insert block receives two byte-wide 77.76 MHz data from the line, which nominally represents two STS-12 streams (A and B). Transport overhead bytes are then optionally inserted into these streams and the streams are forwarded to the HSI. All byte timing pulses required to isolate individual overhead bytes (e.g., A1, A2, B1, D1— ...
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... That byte and all subsequent bytes to be scrambled are exclusive ORed, with the output from the byte-wise scram- bler. The scrambler runs continuously from that byte on throughout the remainder of the frame. A1, A2, J0, and Z0 bytes are not scrambled. Agere Systems Inc. TTSV02622 STS-24 Backplane Transceiver (continued ...
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... TTSV02622 STS-24 Backplane Transceiver Receiver Block EVEN/ODD PARITY (SOFT CTL) PROT SWITCH CH#1—2 PAR ERR ENA MUX INSERT (SOFT CTL) (SOFT CTL) (SOFT CTL) PROT SWITCH LINE PAR ERR FUNCTION HI-Z LPBK FLAG (SOFT CTL) (SOFT CTL) (TO TX) (SOFT REG) PROT SWITCH ...
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... Framer Subblock (Backplane to Line) Framer State Machine Figure 9 shows the state machine that controls the framer. Since the TTSV02622 is intended for use between ASICs via a backplane, there is only one errored frame state; thus, after two transitions are missed, the state machine goes into the OOF state and there is no SEF or LOF indication. ...
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... TTSV02622 STS-24 Backplane Transceiver Receiver Block (continued) Framer Subblock (Backplane to Line) EXPECT A1/A2 & FIND A1/A2 FRAME CONFIRM - FIND A1/A2 TRANSITION - LOCK BARREL SHIFTER - SET ROW/COL/STS COUNTERS Notes: Row, column, and STS counters are only set/reset by state transition from OOF to frame confirm. Expect A1/A2 means that row/col/STS counter values indicate time for last (twelfth) A1 byte. ...
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... Internal Parity Generation An even parity is generated on all data bytes and is routed in parallel with the data to be checked before the protec- tion switch MUX at the parallel output. Agere Systems Inc. TTSV02622 STS-24 Backplane Transceiver ...
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... The pointer mover simply maps incoming frames to the line framing. The K1/K2 bytes and H1—SS bits are also passed through to the pointer generator so that the line can receive them. The mover will handle both concatena- tions inside the STS-12, and to other STS-12s inside the TTSV02622. Pointer Interpreter State Machine The pointer interpreter is minimized as much as possible to keep the gate count low. In keeping with that goal, the pointer interpreter has only three states (NORM, AIS, and CONC). The interpreter’ ...
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... H1 byte = 1001 + single bit error) and offset = 11_1111_1111. AIS pointer offset and N bits are all 1s (SS bits are ignored). NORM pointer (offset 0—782) and (NDF or NRMNBITS). Agere Systems Inc. TTSV02622 STS-24 Backplane Transceiver (continued) STS-9c STS-12c STS-15c SPE SPE ...
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... TTSV02622 STS-24 Backplane Transceiver Receiver Block (continued) Pointer Mover Subblock (Backplane to Line) NORM State. This state will begin whenever two consecutive NORM pointers are received. If two consecutive NORM pointers are received, such that both differ from the current offset, then the current offset will be reset to the last received NORM pointer ...
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... In an attempt to minimize the complexity required from the pointer processor that may be hooked-up to the TTSV02622 parallel output port, two signals (per channel) must be provided to the external world; these are called SPE and C1J1. These two signals will allow a pointer processor to extract payload without interpreting the point- ers ...
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... ISREG bits from other registers. A direct result of the fact that each bit of the ISREG is a logical OR function means that it will have a read value any of the consolidation signals are of value 1, and will be of value 0 if and only if all consolidation signals are of value 0. In the TTSV02622 chip, all ISREG reset values are 0. ...
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... ADDR values delimited by a comma indicate the address for each of two channels, from channel For example, the register for Tx control signals has addresses of 20 and 38. This indicates that channel 1 Tx control signals are at address 20 and channel 2 Tx control signals are at address 38. † Reserved. Agere Systems Inc. TTSV02622 STS-24 Backplane Transceiver DB5 DB4 DB3 FIXED ID MSB ...
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... TTSV02622 STS-24 Backplane Transceiver Registers (continued) Register Map (continued) Table 6. Register Map (continued) * ADDR Reg. DB7 DB6 [6:0] Type 20, 38 CREG HI-Z HI-Z CONTROL OF CONTROL TOH DATA OF OUTPUT PARALLEL OUTPUT BUS 21, 39 CREG Tx MODE OF Tx E1/F1/E2 OPERATION SOURCE SELECT 22, 3A CREG SOURCE SOURCE ...
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... ADDR values delimited by a comma indicate the address for each of two channels, from channel For example, the register for Tx control signals has addresses of 20 and 38. This indicates that channel 1 Tx control signals are at address 20 and channel 2 Tx control signals are at address 38. † Reserved. Agere Systems Inc. TTSV02622 STS-24 Backplane Transceiver DB5 DB4 DB3 Channel Register Block (continued) † ...
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... MSB and LOCKREG LSB values are not set to A0 and 01 respectively, then any values written to the registers in memory locations 06—7F will be ignored. After reset (both hard and soft), the TTSV02622 chip write locked mode. The TTSV02622 chip needs to be unlocked before it can be written to. ...
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... TTSV02622 STS-24 Backplane Transceiver Type Description Device Register Blocks CREG loopback LVDS loopback, transmit to receive on. CREG This control signal is untracked in the TTSV02622 chip scratch bit, and its value has no effect on the TTSV02622 chip. CREG EXT PORT EXT SW EN PROT SW ...
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... TTSV02622 STS-24 Backplane Transceiver Register Descriptions (continued) Table 7. Register Description (continued) Address Bit Name (hex SERIAL PORT OUTPUT MUX SELECT FOR PARALLEL PORT OUTPUT MUX SELECT FOR [7:4] 0A [4:0] FIFO ALIGNER THRESHOLD VALUE (min) [7:5] 0B [4:0] FIFO ALIGNER THRESHOLD VALUE ...
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... VALUE 0F [7:0] TRANSMIT B1 ERROR INSERT MASK Agere Systems Inc. TTSV02622 STS-24 Backplane Transceiver Type Description Device Register Blocks (continued) CREG These three (0C, 0D, and 0E) per-device control signals are used in conjunction with the per channel A1/A2 ERROR INSERT COMMAND control bits to force A1/A2 errors in the transmit direction. ...
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... This condition is continuously moni- tored. If the TTSV02622 memory map has not been unlocked (by writing a 001 to the lock registers), and any address other than the LOCKREG registers or SCRATCH PAD register is written to, then a WRITE TO LOCKED REGIS- TER event will be generated ...
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... SELECT 6 Tx E1/F2/E2 SOURCE SELECT 7 Tx MODE OF OPERATION Agere Systems Inc. TTSV02622 STS-24 Backplane Transceiver Type Description Channel Register Blocks CREG 0 = When Rx direction OOF occurs, do not insert AIS- When Rx direction OOF occurs, insert AIS-L. CREG not force AIS- Force AIS-L. CREG not insert a parity error. ...
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... TTSV02622 STS-24 Backplane Transceiver Register Descriptions (continued) Table 7. Register Description (continued) Address Bit Name (hex) 22 SOURCE SELECT SOURCE SELECT SOURCE SELECT SOURCE SELECT SOURCE SELECT SOURCE SELECT SOURCE SELECT SOURCE SELECT 23, 3B ...
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... ENABLE/MASK REGISTER [7:3] Agere Systems Inc. TTSV02622 STS-24 Backplane Transceiver Type Channel Register Blocks (continued) SREG The value 1 in any bit location indicates that STS CONCAT mode indicates that the STS is not in CON- CAT mode the head of a concatenation group. ...
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... TTSV02622 STS-24 Backplane Transceiver Register Descriptions (continued) Table 7. Register Description (continued) Address Bit Name (hex) 28 FIFO ALIGNER THRESHOLD ERROR FLAG 1 RECEIVER INTER- NAL PATH PARITY ERROR FLAG 2 LOF FLAG 3 LVDS LINK B1 PAR- ITY ERROR FLAG 4 INPUT PARALLEL BUS PARITY ERROR ...
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... ENABLE/MASK AIS INTERRUPT FLAG 8 7 ENABLE/MASK AIS INTERRUPT FLAG 11 Agere Systems Inc. TTSV02622 STS-24 Backplane Transceiver Type Channel Register Blocks (continued) IAREG These are the AIS-P ALARM FLAGs. IAREG These are the AIS-P ALARM FLAGs. IAREG These are the AIS-P ALARM FLAGs. ...
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... TTSV02622 STS-24 Backplane Transceiver Register Descriptions (continued) Table 7. Register Description (continued) Address Bit Name (hex) 2E OVERFLOW FLAGS OVERFLOW FLAGS OVERFLOW FLAGS OVERFLOW FLAGS 12 [7:4] 2F OVERFLOW FLAGS OVERFLOW FLAGS OVERFLOW FLAGS OVERFLOW FLAGS 10 ...
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... A1/A2 FRAME ERROR COUNTER 7 OVERFLOW Agere Systems Inc. TTSV02622 STS-24 Backplane Transceiver Type Channel Register Blocks (continued) IEREG These are the AIS-P ALARM FLAGs. IEREG These are the AIS-P ALARM FLAGs. IEREG These are the AIS-P ALARM FLAGs. IEREG These are the AIS-P ALARM FLAGs. ...
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... Minimum HBM Threshold Minimum CDM on the corner pins only and the LU Minimum CDM on all other pins Recommended Operating Conditions The following tables list the voltages required for proper operation of the TTSV02622 device, along with their toler- ances. Table 10. Recommended Operating Conditions Parameter ...
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... June 2003 Thermal Characteristics The TTSV02622 6.49 mm die in the 272-pin PBGA (2-layer BGA). For thermal characteristics, the following values should be used 15.38 °C 25.09 °C 31.92 °C 1.00 °C/W Table 11. Thermal Resistance—Junction to Ambient Air Speed in Linear Feet per Minute (LFPM) JEDEC Standard Natural Convection ...
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... IEEE document pertained to just the buffer itself; rather they are system-level specifications. LVDS buffers in the TTSV02622 are compliant to all parts of the IEEE 1596.3 spec that pertain to silicon implementation. Unused inputs will not oscillate when they are open or short-circuited. Both P and N terminals of an input pad should not be held at voltages lower than 2 ...
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... June 2003 LVDS I/O (continued) LVDS DRIVER Figure 11. LVDS Driver and Receiver and Associated Internal Components DRIVER Agere Systems Inc. TTSV02622 STS-24 Backplane Transceiver 100 CENTER TAP EXTERNAL DEVICE PINS INTERCONNECT GPD Figure 12. LVDS Driver and Receiver ...
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... TTSV02622 STS-24 Backplane Transceiver LVDS I/O (continued) LVDS Receiver Buffer Capabilities A disabled or unpowered LVDS receiver can withstand a driving LVDS transmitter over the full range of driver oper- ating range, for an unlimited period of time, without being damaged. Table 16 illustrates LVDS driver dc data, Table 17 the ac data, and Table 14 on page 52 and Table 15 on page 52 the LVDS receiver data. ...
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... V—3 °C—125 °C, slow—fast process. DD Table 18. LVDS Driver Reference Data Parameter REF10 Voltage Range REF14 Voltage Range Nominal Input Current— REF10 and REF14 Reference Inputs Agere Systems Inc. TTSV02622 STS-24 Backplane Transceiver Symbol Conditions 100 OH LOAD V ...
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... Clock and Data Recovery (CDR) The following specifications are in reference to the clock and data recovery macro that is used for the backplane interface on the TTSV02622 chip. Input Data 622 Mbits/s scrambled data stream conforms to SONET STS-12 and SDH STM-4 data format using either a PN7 or PN9 sequence ...
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... Clock Period P T Clock Low Time L T Clock High Time H T Data Setup Time SU T Data Hold Time HD Agere Systems Inc. TTSV02622 STS-24 Backplane Transceiver FIRST A1 OF STS Figure 14. Input Parallel Port Timing Parameter Min Typ ...
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... TTSV02622 STS-24 Backplane Transceiver Timing Characteristics (continued) SYS_CLK SYS_FP PARALLEL DATA INPUT BUS LVDS DATA OUT Table 21. Transmitter Transport Delay Timing Requirements Symbol T Number of Clocks of Delay from Parallel Bus Input to LVDS Output PROP Notes: LVDS data transmitted MSB first. Min/max variation due to clock phase selected in clock recovery block. ...
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... Data Setup Time SU T Data Hold Time HD T Clock to Output Time of Data, Parity, SPE, and C1J1 Pins CO Note: Min T number is calculated based load. Max T CO Agere Systems Inc. TTSV02622 STS-24 Backplane Transceiver FIRST A1 OF STS-1 #1 Figure 16 ...
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... TTSV02622 STS-24 Backplane Transceiver Timing Characteristics (continued) SYS_CLK PROT_SW_A OUTPUT BUS* A SYS_CLK OUTPUT BUS A & B Table 23. Protection Switch Timing Requirements Symbol T Transport Delay from Latching of PROT_SW_A to Actual Data TR Switch T Transport Delay from Latching of PROT_SW_A to Actual Data HIZ HI-Z T Propagation Delay from SYS_CLK to HI_Z of Output Bus ...
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... Clock Period P T Clock High Time HI T Clock Low Time LO T Data Setup Time S T Data Hold Time H Agere Systems Inc. TTSV02622 STS-24 Backplane Transceiver ROW #1 1044 bytes SPE GUARD BAND (4 TOH CLK BIT BYTE STS-1 #1 Figure 18 ...
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... TTSV02622 STS-24 Backplane Transceiver Timing Characteristics (continued) INPUT LVDS SERIAL 622 Mbits/s 36 bytes TOH DATA T TRANS_TOH TOH_CLK RX TOH TOH CLK ENA TOH SERIAL OUTPUT MSBIT( BYTE STS-1 #1 Table 25. Output Serial Port Timing Requirements Symbol T Data Clock to Out CO T Delay from First A1 LVDS Serial Input to Transfer to ...
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... ACCESS_MIN T Maximum Time from Register FF to Pad INT_MAX Minimum Hold Time that RD_WR_N, ADDR, and DB Must RD_WR_N ADDR_MAX DB_HOLD Agere Systems Inc. TTSV02622 STS-24 Backplane Transceiver T ACCESS_MIN T RD_WR_N, ADDR_MAX, DB_HOLD DATA VALID OLD VALUE NEW VALUE T WRITE_MAX Figure 20. Write Transaction Parameter ...
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... TTSV02622 STS-24 Backplane Transceiver Timing Characteristics (continued) CPU Interface Timing (continued) CS_N RD_WR_N ADDR[6:0] DB[7:0] T ADDR_MAX T RD_WR_MAX Table 27. Read Transaction Timing Requirements Symbol T Minimum Pulse Width for CS_N PULSE T Maximum Time from Negative Edge of CS_N to Addr Valid ADDR_MAX T Maximum Time from Negative Edge of CS_N to RD_WR_N Rising ...
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... PWB 0.36 0.60 0. CENTER ARRAY E FOR THERMAL D ENHANCEMENT C (OPTIONAL BALL CORNER Agere Systems Inc. TTSV02622 STS-24 Backplane Transceiver 27.00 0.20 +0.70 24.00 –0.00 1.17 0.04 SOLDER BALL 19 SPACES @ 1.27 = 24. +0.70 24.00 –0.00 27.00 0.20 0.05 2.13 0.19 SEATING PLANE 0.20 0.75 0.15 19 SPACES @ 1 ...
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... TTSV02622 STS-24 Backplane Transceiver Ordering Information Device Code TTSV02622V2-DB For additional information, contact your Agere Systems Account Manager or the following: INTERNET: http://www.agere.com E-MAIL: docmaster@agere.com N. AMERICA: Agere Systems Inc., Lehigh Valley Central Campus, Room 10A-301C, 1110 American Parkway NE, Allentown, PA 18109-9138 1-800-372-2447, FAX 610-712-4106 (In CANADA: 1-800-553-2448, FAX 610-712-4106) ASIA: Agere Systems Hong Kong Ltd., Suites 3201 & ...