ttsv02622 ETC-unknow, ttsv02622 Datasheet - Page 40

• Manufacturer Part Number: ttsv02622
• Description: Sts-24 Backplane Transceiver
• Manufacturer: ETC-unknow

TTSV02622 STS-24 Backplane Transceiver
Register Descriptions
Table 7. Register Description (continued)
40
Address
(hex)
10
11
12
13
[3:2]
[7:5]
[4:0]
[7:5]
[7:2]
[1:0]
[7:2]
Bit
0
1
4
0
1
WRITE TO LOCKED
REGISTER ERROR
PER DEVICE INT
FRAME OFFSET
ERRROR FLAG
ENABLE/MASK
ENABLE/MASK
REGISTER
REGISTER
CH 1 INT
CH 2 INT
Name
FLAG
(continued)
Device Register Blocks (continued)
ISREG Consolidation interrupts.
ISREG Consolidation interrupts.
ISREG Consolidation interrupts.
IEREG
IAREG If in the receive direction the phase offset between any
IAREG See address 0x12 bit 0 description.
IEREG See address 0x12 bit 0 description.
Type
0 = No interrupt.
1 = Interrupt.
0 = No interrupt.
1 = Interrupt.
0 = No interrupt.
1 = Interrupt.
two channels exceeds 17 bytes, then a frame offset error
event will be issued. This condition is continuously moni-
tored.
If the TTSV02622 memory map has not been unlocked
(by writing a 001 to the lock registers), and any address
other than the LOCKREG registers or SCRATCH PAD
register is written to, then a WRITE TO LOCKED REGIS-
TER event will be generated.
Reserved.
Reserved.
Reserved.
Reserved.
Reserved.
Description
Agere Systems Inc.
June 2003
Reset
Value
(hex)
00
00
00
00
00
00
00