hi-8589pqt Holt Integrated Circuits, Inc., hi-8589pqt Datasheet
hi-8589pqt
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hi-8589pqt Summary of contents
Page 1
... BD15 - 7 BD14 - 8 BD13 - 9 BD12 - 10 BD11 - 11 HOLT INTEGRATED CIRCUITS www.holtic.com ARINC 429 (Top View HI-8581PQI HI-8589PQI - 5 & HI-8581PQT HI-8589PQT 44-Pin Plastic Quad Flat Pack (PQFP) (See page 12 for additional pin configurations ENTX TXB(OUT TXA(OUT GND PL2 24 - PL1 23 - ...
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... Data Bus Data Bus Data Bus Transmitter ready flag. Goes low when ARINC word loaded into FIFO. Goes high after transmission and FIFO empty. Latch enable for byte 1 entered from data bus to transmitter FIFO. Latch enable for byte 2 entered from data bus to transmitter FIFO. Must follow ...
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... FUNCTIONAL DESCRIPTION CONTROL WORD REGISTER Both the HI-8581and HI-8589 contain 10 data flip flops whose D inputs are connected to the data bus and clocks connected to CWSTR . Each flip flop provides options to the user as follows: DATA BUS FUNCTION CONTROL PIN If enabled, the transmitter’s digital ...
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... To qualify data bits, One or Zero in the upper bits of the sampling shift register must be followed by Null in the lower bits within the data bit time. A word gap Null re- quires three consecutive Nulls in both the upper and lower bits of the sampling shift register. This guarantees the mini- mum pulse width ...
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... The parity generator counts the ONES in the 31-bit word. If the BD12 control word bit is set low, the 32nd bit transmitted will make parity odd. If the control bit is high, the parity is even. SELF TEST If the BD05 control word bit is set low, the digital outputs of the ...
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... Each ARINC input pin must be connected to the ARINC bus through a 10 Kohm resistor in order for the chip to properly detect the correct ARINC levels. The typical 10 volt differential signal is The translated and input to a window comparator and latch. The comparator levels are set so that with the external 10 Kohm resistors, they are just below the standard 6 ...
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... BYTE SELECT SEL ENABLE BYTE ON BUS EN DATA BUS DATA BUS PL1 PL2 TX/R PL2 t PL2EN TX/R ENTX t ENDAT TXA(OUT) TXB(OUT) V DIFF (TXA(OUT) - TXB(OUT)) 10% one level HI-8581, HI-8589 RECEIVER OPERATON t D/R DON'T CARE t SELEN t ENSEL t D/REN BYTE 1 VALID t ENDATA TRANSMITTER OPERATION BYTE 1 VALID t DWSET t DWHLD ...
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... TIMING DIAGRAMS (cont.) BIT 32 429DI D D/R D/REN EN t SELEN SEL DON'T CARE t ENPL PL1 PL2 TX/R ENTX TXA(OUT) TXB(OUT) HI-8581, HI-8589 REPEATER OPERATION TIMING t END ENEN EN t ENSEL t SELEN t PLEN t t PLEN ENPL t TX/REN HOLT INTEGRATED CIRCUITS 8 DON'T CARE t ENSEL ...
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... To GND Vcc C H Input Voltage Input Voltage Input Sink I IH Input Source I IL Input Voltage Input Voltage Input Sink I IH Input Source I IL HOLT INTEGRATED CIRCUITS 9 1.5 W, derate 10mW/ C 1.0 W, derate 7mW/ -65°C to +150°C (Industrial) -40° ...
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... Logic "1" Output Voltage Logic "0" Output Voltage Output Current: (Bi-directional Pins) Output Current: (All Other Outputs) Output Capacitance: Operating Voltage Range Operating Supply Current HI-8581, HI-8589 CONDITIONS SYMBOL V no load and magnitude at pin DOUT V NOUT " " " I OUT ...
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... Spacing - Delay - 32nd ARINC Bit to TX/R HIGH Spacing - TX/R HIGH to ENTX LOW LINE DRIVER OUTPUT TIMING Delay - ENTX HIGH to TXA(OUT) or TXB(OUT): High Speed Delay - ENTX HIGH to TXA(OUT) or TXB(OUT): Low Speed Line driver transition differential times: (High Speed) (Low Speed) REPEATER OPERATION TIMING Delay - TX/R LOW to ENTX HIGH ...
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... D/R2 9 SEL 10 EN1 11 EN2 12 BD15 13 BD14 14 BD13 15 BD12 16 BD11 17 HI-8581PJI / HI-8589PJI HI-8581PJT / HI-8589PJT 44-Pin Plastic J-Lead PLCC ORDERING INFORMATION HI - 8581 PART NUMBER No dash number PART NUMBER PART NUMBER PART NUMBER PART NUMBER HI-8581, HI-8589 39 ENTX 429DI2( N TXB(OUT) ...
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... SQ. .039 ±.005 (.990 ±.127) .019 ±.002 (.483 ± .051) HI-8581, HI-8589 PACKAGE DIMENSIONS PIN NO. 1 IDENT .045 x 45° .653 ±.004 (16.586 ±.102) SQ. See Detail A .610 ±.020 (15.494± ...
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... PLASTIC QUAD FLAT PACK (PQFP) .547 BSC SQ. (13.9) See Detail A .097 max (2.45) BSC = “Basic Spacing between Centers” is theoretical true position dimension and has no tolerance. (JEDEC Standard 95) HI-8581, HI-8589 PACKAGE DIMENSIONS .394 BSC SQ. (10.0) .079 +.004 / -.002 (2.00 +.10 / -.05) HOLT INTEGRATED CIRCUITS 14 inches (millimeters) Package Type: 44PQS .007 max ( ...