l-fw32206t100 ETC-unknow, l-fw32206t100 Datasheet - Page 11

• Manufacturer Part Number: l-fw32206t100
• Description: 1394a Phy/link Open Host Controller
• Manufacturer: ETC-unknow

Data Sheet, Rev. 1
December 2005
FW322 Functional Description
Link Core
The link core shown in Figure 4 consists of the following blocks:
Agere Systems Inc.
Link Control State Machine: main link state machine that controls all other link core modules.
Transmit (TX): reads from the AT and IT FIFOs and forms 1394 packets for transmit.
Receive (RX): pipes incoming 1394 packet data to appropriate FIFO (if any).
Address Decoder: decodes the destination ID of an incoming 1394 packet to determine if an acknowledge is
needed.
CRC: calculates and checks CRC on outgoing and incoming packets.
Isochronous Control Timer: contains the logic for the 1394 cycle timer.
DataMUX: pipes 1394 data to and from various modules.
Interface Control: contains interrupt and registers for the link core. Interfaces with the slave control block of the
PCI core.
PHY-Link Interface: interfaces with the 1394 physical layer.
AT FIFO
AR FIFO
IT FIFO
IR FIFO
PCI SLAVE
INTERFACE
CONTROL
TX
RX
DECODER
ADDRESS
CRC
Figure 4. Link Core Block Diagram
(continued)
CONTROL
DATAMUX
LINK CONTROL
ISOCH
TIMER
1394a PCI PHY/Link Open Host Controller
MACHINE
STATE
INTERFACE
PHY - LINK
FW322 06 T100
PHYDATA
PHYCTL
PHYLREQ
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